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Practical low power digital VLSI designJanuary 1998
- Author:
- Gary K. Yeap
Abstract
No abstract available.
Cited By
- Musiiwa P and Akashe S (2018). Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells, Wireless Personal Communications: An International Journal, 99:1, (47-66), Online publication date: 1-Mar-2018.
Musiiwa P and Akashe S Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies, (1-6)- Brandon A and Wong S Support for dynamic issue width in VLIW processors using generic binaries Proceedings of the Conference on Design, Automation and Test in Europe, (827-832)
- Vaidya S and Dandekar D A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematics Proceedings of the 2011 International Conference on Communication, Computing & Security, (383-386)
- Sasilatha T and Raja J (2011). Modified Design and Analysis of a CMOS LNA for Wireless Sensor Network Applications, Wireless Personal Communications: An International Journal, 57:4, (655-669), Online publication date: 1-Apr-2011.
- Callou G, Maciel P, Tavares E, Andrade E, Nogueira B, Araujo C and Cunha P (2011). Energy consumption and execution time estimation of embedded system applications, Microprocessors & Microsystems, 35:4, (426-440), Online publication date: 1-Jun-2011.
- Barenghi A, Pelosi G and Teglia Y Improving first order differential power attacks through digital signal processing Proceedings of the 3rd international conference on Security of information and networks, (124-133)
- Chen D, Cong J, Dong C, He L, Li F and Peng C (2010). Technology mapping and clustering for FPGA architectures with dual supply voltages, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29:11, (1709-1722), Online publication date: 1-Nov-2010.
- Junior M, Neto S, Maciel P, Lima R, Ribeiro A, Barreto R, Tavares E and Braga F Analyzing software performance and energy consumption of embedded systems by probabilistic modeling Proceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency, (261-281)
- Huang Z and Ercegovac M (2005). High-Performance Low-Power Left-to-Right Array Multiplier Design, IEEE Transactions on Computers, 54:3, (272-283), Online publication date: 1-Mar-2005.
- Takahashi O, Cook R, Cottier S, Dhong S, Flachs B, Hirairi K, Kawasumi A, Murakami H, Noro H, Oh H, Onish S, Pille J and Silberman J The circuit design of the synergistic processor element of a CELL processor Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, (111-117)
- Raja T, Agrawal V and Bushnell M Design of variable input delay gates for low dynamic power circuits Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (436-445)
- Takahashi O, Cottier S, Dhong S, Flachs B and Silberman J (2005). Power-Conscious Design of the CELL Processor's Synergistic Processor Element, IEEE Micro, 25:5, (10-18), Online publication date: 1-Sep-2005.
- Anderson J, Najm F and Tuan T Active leakage power optimization for FPGAs Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, (33-41)
- Chen D, Cong J, Li F and He L Low-power technology mapping for FPGA architectures with dual supply voltages Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, (109-117)
- Choi S, Jang J, Mohanty S and Prasanna V (2019). Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures, The Journal of Supercomputing, 26:3, (259-281), Online publication date: 1-Nov-2003.
- Choi S, Scrofano R, Prasanna V and Jang J Energy-efficient signal processing using FPGAs Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, (225-234)
- Anderson J and Najm F Switching activity analysis and pre-layout activity prediction for FPGAs Proceedings of the 2003 international workshop on System-level interconnect prediction, (15-21)
- Glökler T, Hoffmann A and Meyr H (2003). Methodical Low-Power ASIP Design Space Exploration, Journal of VLSI Signal Processing Systems, 33:3, (229-246), Online publication date: 1-Mar-2003.
- Chen O, Wang S and Wu Y (2003). Minimization of switching activities of partial products for designing low-power multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11:3, (418-433), Online publication date: 1-Jun-2003.
- Shang L, Kaviani A and Bathala K Dynamic power consumption in Virtex™-II FPGA family Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, (157-164)
- Tsui C, Cheng R and Ling C (2019). Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications, Wireless Personal Communications: An International Journal, 14:1, (49-64), Online publication date: 1-Jul-2000.
- Sahoo B, Kuhlmann M and Parhi K A low-power correlator Proceedings of the 10th Great Lakes symposium on VLSI, (153-155)
- Bishop B and Irwin M Databus charge recovery Proceedings of the 1999 international symposium on Low power electronics and design, (85-87)
Index Terms
- Practical low power digital VLSI design
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