- Author:
- Pascal Constantin Hans Meier,
- Adviser:
- Rob Rutenbar
Successively higher levels of device integration in microelectronics have caused reduction of power dissipation to become a primary design goal. In many integrated circuit designs, the multiplier is a critically important block, due to its high latency as well as high power characteristics. In this work, we investigate sources of power dissipation in various implementations of small-bit-width digital multipliers. Techniques such as gate-level architectural designs and latch insertion for minimization of glitching are examined. We assess the utility of several techniques for power reduction, and introduce the application of bit polarity inversion to minimize circuit count. The impact of physical design on multiplier power characteristics is presented, along with an exposition of relevant power and delay trade-offs.
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