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The SPARC architecture manual (version 9)April 1994
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- Baray F, Codognet P, Diaz D and Michel H Code-based test generation for validation of functional processor descriptions Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems, (569-584)
- Settle A, Connors D, Hoflehner G and Lavery D Optimization for the Intel® Itanium® architecture register stack Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, (115-124)
- Scott K, Kumar N, Velusamy S, Childers B, Davidson J and Soffa M Retargetable and reconfigurable software dynamic translation Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, (36-47)
- Sakamoto M, Katsuno A, Inoue A, Asakawa T, Ueno H, Morita K and Kimura Y Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems Proceedings of the 9th International Symposium on High-Performance Computer Architecture
- Martínez J and Torrellas J (2002). Speculative synchronization, ACM SIGOPS Operating Systems Review, 36:5, (18-29), Online publication date: 1-Dec-2002.
- Martínez J and Torrellas J (2002). Speculative synchronization, ACM SIGARCH Computer Architecture News, 30:5, (18-29), Online publication date: 1-Dec-2002.
- Martínez J and Torrellas J Speculative synchronization Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, (18-29)
- Martínez J and Torrellas J (2002). Speculative synchronization, ACM SIGPLAN Notices, 37:10, (18-29), Online publication date: 1-Oct-2002.
- Mauer C, Hill M and Wood D Full-system timing-first simulation Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, (108-116)
- Mauer C, Hill M and Wood D (2002). Full-system timing-first simulation, ACM SIGMETRICS Performance Evaluation Review, 30:1, (108-116), Online publication date: 1-Jun-2002.
- Ramanujam J, Krishnamurthy S, Hong J and Kandemir M Address Code and Arithmetic Optimizations for Embedded Systems Proceedings of the 2002 Asia and South Pacific Design Automation Conference
- Martin M, Sorin D, Cain H, Hill M and Lipasti M Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, (328-337)
- Czajkowski G and Daynès L (2001). Multitasking without comprimise, ACM SIGPLAN Notices, 36:11, (125-138), Online publication date: 1-Nov-2001.
- Czajkowski G and Daynès L Multitasking without comprimise Proceedings of the 16th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, (125-138)
- Lee J and Padua D (2001). Hiding Relaxed Memory Consistency with a Compiler, IEEE Transactions on Computers, 50:8, (824-833), Online publication date: 1-Aug-2001.
- Flood C, Detlefs D, Shavit N and Zhang X Parallel garbage collection for shared memory multiprocessors Proceedings of the 2001 Symposium on JavaTM Virtual Machine Research and Technology Symposium - Volume 1, (21-21)
- Dice D Implementing fast javaTM monitors with relaxed-locks Proceedings of the 2001 Symposium on JavaTM Virtual Machine Research and Technology Symposium - Volume 1, (13-13)
- Golshan F Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC"-III Microprocessor Proceedings of the 2000 IEEE International Test Conference
- Bacon D, Strom R and Tarafdar A (2000). Guava, ACM SIGPLAN Notices, 35:10, (382-400), Online publication date: 1-Oct-2000.
- Maessen J and Shen X (2000). Improving the Java memory model using CRF, ACM SIGPLAN Notices, 35:10, (1-12), Online publication date: 1-Oct-2000.
- Bacon D, Strom R and Tarafdar A Guava Proceedings of the 15th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, (382-400)
- Maessen J and Shen X Improving the Java memory model using CRF Proceedings of the 15th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, (1-12)
- Hill M, Condon A, Plakal M and Sorin D A system-level specification framework for I/O architectures Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures, (138-147)
- Pugh W Fixing the Java memory model Proceedings of the ACM 1999 conference on Java Grande, (89-98)
- Sanchez E, Haenni J, Beuchat J, Stauffer A, Perez-Uribe A and Sipper M (1999). Static and Dynamic Configurable Systems, IEEE Transactions on Computers, 48:6, (556-564), Online publication date: 1-Jun-1999.
- Shen X, Arvind and Rudolph L Commit-reconcile & fences (CRF) Proceedings of the 26th annual international symposium on Computer architecture, (150-161)
- Shen X, Arvind and Rudolph L (1999). Commit-reconcile & fences (CRF), ACM SIGARCH Computer Architecture News, 27:2, (150-161), Online publication date: 1-May-1999.
- Horel T and Lauterbach G (1999). UltraSPARC-III, IEEE Micro, 19:3, (73-85), Online publication date: 1-May-1999.
- Ip C and Dill D (1999). Verifying Systems with Replicated Components in Mur𝛟, Formal Methods in System Design, 14:3, (273-310), Online publication date: 1-May-1999.
- Clinger W, Hartheimer A and Ost E (1999). Implementation Strategies for First-Class Continuations, Higher-Order and Symbolic Computation, 12:1, (7-45), Online publication date: 1-Apr-1999.
- Park S and Dill D (1999). An Executable Specification and Verifier for Relaxed Memory Order, IEEE Transactions on Computers, 48:2, (227-235), Online publication date: 1-Feb-1999.
- Lynch W, Lauterbach G and Chamdani J (1998). Low load latency through sum-addressed memory (SAM), ACM SIGARCH Computer Architecture News, 26:3, (369-379), Online publication date: 1-Jun-1998.
- Ghughal R, Mokkedem A, Nalumasu R and Gopalakrishnan G Using “test model-checking” to verify the Runway-PA8000 memory model Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures, (231-239)
- Lynch W, Lauterbach G and Chamdani J Low load latency through sum-addressed memory (SAM) Proceedings of the 25th annual international symposium on Computer architecture, (369-379)
- Henkel J and Li Y Energy-conscious HW/SW-partitioning of embedded systems Proceedings of the 6th international workshop on Hardware/software codesign, (23-27)
- Normoyle K, Csoppenszky M, Tzeng A, Johnson T, Furman C and Mostoufi J (1998). UltraSPARC-IIi, IEEE Micro, 18:2, (14-24), Online publication date: 1-Mar-1998.
- Pong F, Browne M, Nowatzyk A, Dubois M and Aybay G (1998). Design Verification of the S3.mp Cache-Coherent Shared-Memory System, IEEE Transactions on Computers, 47:1, (135-140), Online publication date: 1-Jan-1998.
- Teodosiu D, Baxter J, Govil K, Chapin J, Rosenblum M and Horowitz M Hardware fault containment in scalable shared-memory multiprocessors Proceedings of the 24th annual international symposium on Computer architecture, (73-84)
- Ranganathan P, Pai V and Adve S Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures, (199-210)
- Teodosiu D, Baxter J, Govil K, Chapin J, Rosenblum M and Horowitz M (1997). Hardware fault containment in scalable shared-memory multiprocessors, ACM SIGARCH Computer Architecture News, 25:2, (73-84), Online publication date: 1-May-1997.
- Pai V, Ranganathan P, Adve S and Harton T (1996). An evaluation of memory consistency models for shared-memory systems with ILP processors, ACM SIGOPS Operating Systems Review, 30:5, (12-23), Online publication date: 1-Dec-1996.
- Adve S and Gharachorloo K (1996). Shared Memory Consistency Models, Computer, 29:12, (66-76), Online publication date: 1-Dec-1996.
- Pai V, Ranganathan P, Adve S and Harton T An evaluation of memory consistency models for shared-memory systems with ILP processors Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, (12-23)
- Pai V, Ranganathan P, Adve S and Harton T (1996). An evaluation of memory consistency models for shared-memory systems with ILP processors, ACM SIGPLAN Notices, 31:9, (12-23), Online publication date: 1-Sep-1996.
- Tremblay M, O'Connor J, Narayanan V and He L (1996). VIS Speeds New Media Processing, IEEE Micro, 16:4, (10-20), Online publication date: 1-Aug-1996.
- Mukherjee S, Falsafi B, Hill M and Wood D Coherent network interfaces for fine-grain communication Proceedings of the 23rd annual international symposium on Computer architecture, (247-258)
- Mukherjee S, Falsafi B, Hill M and Wood D (1996). Coherent network interfaces for fine-grain communication, ACM SIGARCH Computer Architecture News, 24:2, (247-258), Online publication date: 1-May-1996.
- Tremblay M and O'Connor J (1996). UltraSparc I, IEEE Micro, 16:2, (42-50), Online publication date: 1-Apr-1996.
- Goldman G and Tirumalai P UltraSPARC-II Proceedings of the 41st IEEE International Computer Conference
- Tirumalai P, Greenley D, Beylin B and Subramanian K UltraSPARC Proceedings of the 41st IEEE International Computer Conference
- Hamblen J, Owen H, Yalamanchili S and Dao B Using rapid prototyping in computer architecture design laboratories Proceedings of the 1996 workshop on Computer architecture education, (4-es)
- Park S and Dill D An executable specification, analyzer and verifier for RMO (relaxed memory order) Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures, (34-41)
- Panwar R and Rennels D Reducing the frequency of tag compares for low power I-cache design Proceedings of the 1995 international symposium on Low power design, (57-62)
- Tremblay M, Maturana G, Inoue A and Kohn L A fast and flexible performance simulator for micro-architecture trade-off analysis on UltraSPARC-I Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, (2-6)
- Skudlarek J (1994). Remarks on A methodology for implementing highly concurrent data, ACM SIGPLAN Notices, 29:12, (87-93), Online publication date: 1-Dec-1994.
- Barach D, Kohli J, Slice J, Spaulding M, Bharadhwaj R, Hudson D, Neighbors C, Saxena N and Crunk R (1994). HALSIM—a very fast SPARC V9 behavioral model, ACM SIGARCH Computer Architecture News, 22:1, (52-58), Online publication date: 1-Mar-1994.
- Kubiatowicz J and Agarwal A Anatomy of a message in the Alewife multiprocessor Proceedings of the 7th international conference on Supercomputing, (195-206)
- Hamilton G and Kougiouris P The spring nucleus Proceedings of the USENIX Summer 1993 Technical Conference on Summer technical conference - Volume 1, (1-15)
Index Terms
- The SPARC architecture manual (version 9)
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