The Sparc T4 is the next generation of Oracle's multicore, multithreaded 64-bit Sparc server processor. It delivers significant performance improvements over its predecessor, the Sparc T3 processor. The authors describe Sparc T4's key features and ...
MICRO 30: Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The performance of Very Long Instruction Word (VLIW) microprocessors depends on the close cooperation between the compiler and the architecture. This paper evaluates a set of important compilation techniques and related architectural features for VLIW ...
SPAA '06: Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Our general goal is to port programs from one multiprocessor architecture to another, while ensuring that each program's semantics remains unchanged. This paper addresses a subset of the problem by determining the relationships between memory ...
Sun Microsystems' SPARC (Scalable Processor ARChitecture) has been in use since 1987, substantially revised once, and implemented at least a dozen times by several chip makers, and is under the control of a multi-vendor consortium. By the early 1990s, it was obvious that it did not meet all the requirements of this decade, and the current technology could support an architecture that did meet them. Hence, it was necessary to define a new version of SPARC.
This tape begins with a brief recap of SPARC versions 7 and 8. (Versions 1 through 6 were never released.) It then moves quickly into Ditzel's view of the extensions that were required in order to meet new needs. Some system architects might disagree with part of this list, but most of it (more than 32 address bits, for example) is indisputable. Not surprisingly, the list of needs matches the list of architectural changes.
This match is not a deliberate attempt to manipulate viewers of this tape. Rather, any process of this sort creates a self-fulfilling prophecy. If designers think X is important, they will add X, so the additions will by definition meet their perceived needs. What of it if different designers would see a different set of needs__?__ Let them design their own chip.
The list of requirements for SPARC Version 9 included upward user-mode compatibility with earlier versions, a larger address space, better operating system support, better support for other advanced software concepts (such as lightweight threads and objects) and hardware advances (including superscalar implementations and multiprocessors), and the potential for higher performance. Ditzel discusses how SPARC Version 9 achieves these, spending the most time on 64-bit addressing and its implications. SPARC's approach conceptually resembles the way Data General extended its Eclipse line from 16 to 32 bits: it doubled the size of the existing registers, let old instructions use their low-order halves, and added new instructions to manipulate their full length.
Ditzel also addresses a few features that were deliberately but not cavalierly left out of SPARC Version 9: decimal arithmetic, character string operation<__?__Pub Caret>s, instructions to load 64-bit constants, and a multiply-add instruction. Finally, he compares SPARC Version 9 with some other recent well-known architectures, such as Digital's Alpha and Mips Computer's R4000. It is not surprising that, measured against his list of priorities, SPARC Version 9 comes out on top. One suspects that the other systems' designers might feel differently, but this is not their tape.
While the tape is well organized, its structure is not obvious at first viewing. It moves from one topic to the next without a clear sense of direction. A better introduction, or an accompanying written outline, would help. As it stands, an instructor using this tape for a class should create a written outline ahead of time, then use it to explain to the students what they will see and in what order.
Ditzel speaks clearly and at a good speed: not too fast to follow or so slowly as to bore the listener. The tape is, however, short on graphics, which is unfortunate for such a visual medium. It contains one diagram, used to explain why both 32-bit and 64-bit right arithmetic shift instructions are necessary, three short examples of C code, and a few examples of SPARC assembly code. The rest of the time, the viewer watches slides of summary text or Ditzel's face, which often seems to be peeking at notes on an unseen desk. David Patterson's earlier (Version 7) SPARC tape [1], also in this series, is better in both respects: he uses graphics to good effect, and he moves around. Incidentally, it is a good idea to view that tape before this unless one is already familiar with, at least, basic RISC concepts.
Computer architects interested in SPARC or RISC, colleges or universities offering courses in computer architecture, system developers using SPARC or competing with it, and SPARC programmers can all benefit from this tape. At a price of around $35, they (or their employers) should also be able to afford it.
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