Browse Books

Jin Y and Li P (2017). Performance and robustness of bio-inspired digital liquid state machines, Neurocomputing, 226:C, (145-160), Online publication date: 22-Feb-2017.

Sun J, Talarico C, Gupta P and Roveda J (2015). A New Uncertainty Budgeting-Based Method for Robust Analog/Mixed-Signal Design, ACM Transactions on Design Automation of Electronic Systems, 21:1, (1-25), Online publication date: 2-Dec-2015.

Gawish E, El-Kharashi M and Abu-Elyazeed M (2014). Variability-tolerant routing algorithms for Networks-on-Chip, Microprocessors & Microsystems, 38:8, (1037-1045), Online publication date: 1-Nov-2014.

Alioto M and Esseni D Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, (1-6)

Majzoobi M, Kong J and Koushanfar F (2013). Low-power resource binding by postsilicon customization, ACM Transactions on Design Automation of Electronic Systems, 18:2, (1-22), Online publication date: 1-Mar-2013.

Sun J, Gupta P and Roveda J A new uncertainty budgeting based method for robust analog/mixed-signal design Proceedings of the 49th Annual Design Automation Conference, (529-535)

Pons M, Morgan M and Piguet C Fixed origin corner square inspection layout regularity metric Proceedings of the Conference on Design, Automation and Test in Europe, (1397-1402)

Raji M, Tajary A, Ghavami B, Pedram H and Zarandi H Statistical leakage power optimization of asynchronous circuits considering process variations Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation, (126-136)

Alioto M, Palumbo G and Pennisi M (2019). Understanding the effect of process variations on the delay of static and domino logic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18:5, (697-710), Online publication date: 1-May-2010.

Rithe R, Gu J, Wang A, Datla S, Gammie G, Buss D and Chandrakasan A Non-linear operating point statistical analysis for local variations in logic timing at low voltage Proceedings of the Conference on Design, Automation and Test in Europe, (965-968)

Hernández C, Silla F and Duato J A methodology for the characterization of process variation in NoC links Proceedings of the Conference on Design, Automation and Test in Europe, (685-690)

Cheng L, Gupta P and He L On confidence in characterization and application of variation models Proceedings of the 2010 Asia and South Pacific Design Automation Conference, (751-756)

Kouretas I and Paliouras V Residue arithmetic for variation-tolerant design of multiply-add units Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (26-35)

Raji M, Ghavami B, Zarandi H and Pedram H Process variation aware performance analysis of asynchronous circuits considering spatial correlation Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (5-15)

Orshansky M and Wang W (2009). Statistical analysis of circuit timing using majorization, Communications of the ACM, 52:8, (95-100), Online publication date: 1-Aug-2009.

Reda S and Nassif S Analyzing the impact of process variations on parametric measurements Proceedings of the Conference on Design, Automation and Test in Europe, (375-380)

Wang X, Tehranipoor M and Datta R Path-RO Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, (640-646)

Long J and Memik S Automated design of self-adjusting pipelines Proceedings of the 45th annual Design Automation Conference, (211-216)