Peter Flake
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Abstract
This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.
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Index Terms
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CASES '02: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systemsChip fabrication technology continues to plunge deeper into sub-micron levels requiring hardware designers to utilize ever-increasing amounts of logic and shorten design time. Toward that end, high-level languages such as C/C++ are becoming popular for ...
The Semantic Challenge of Verilog HDL
LICS '95: Proceedings of the 10th Annual IEEE Symposium on Logic in Computer ScienceThe Verilog hardware description language (HDL) is widely used to model the structure and behavior of digital systems ranging from simple hardware building blocks to complete systems. Its semantics is based on the scheduling of events and the ...
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction
DAC '03: Proceedings of the 40th annual Design Automation ConferenceIn this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating ...
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