S. Rames
ABSTRACT
No abstract available.
- Session details: Timing and performance analysis
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Timing analysis including clock skew
Clock skew is an increasing concern for high-speed circuit designers. Circuit designers use transparent latches and skew-tolerant domino circuits to hide clock skew from the critical path and take advantage of shared portions of the clock network to ...
Session details: Performance and timing analysis
DATE '14: Proceedings of the conference on Design, Automation & Test in EuropeTiming model reduction for hierarchical timing analysis
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided designIn this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, each functional block is characterized into an abstract timing model. The ...
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