Katherine Shu-Min Li
Skip Abstract Section
Abstract
A systematic design methodology is presented for custom Network-on-Chip (NoC) in three-dimensional integrated circuits (3D-ICs). In addition, fault tolerance is supported in the NoC if extra links are included in the NoC topology. In the proposed method, processors and the communication architecture are synthesized simultaneously in the 3D floorplanning process. 3D-IC technology enables ICs to be implemented in smaller size with higher performance; on the flip side, 3D-ICs suffer yield loss due to multiple dies in a 3D stack and lower manufacturing yield of through-silicon vias (TSVs). To alleviate this problem, a known-good-dies (KGD) test can be applied to ensure every die to be packaged into a 3D-IC is fault-free. However, faulty TSVs cannot be tested in the KGD test. In this article, the proposed method deals with the problem by providing fault tolerance in the NoC topology. The efficiency of the proposed method is evaluated using several benchmark circuits, and the experimental results show that the proposed method produces 3D NoCs with comparable performance than previous methods when fault-tolerant features are not realized. With fault tolerance in NoCs, higher yield can be achieved at the cost of performance penalty and elevated power level.
- Luca Benini. 2006. Application specific NoC design. In Proceedings of the IEEE/ACM Design, Automation, and Test in Europe Conference (DATE). 491--495. Google Scholar
Cross Ref
- Tobias Bjerregaard and Shankar Mahadevan. 2006. A survey of research and practices of network-on-chip. ACM Computing Surveys 38, (March 2006), Article 1, 51 pages.Google ScholarDigital Library
- Paul Bogdan, Tudor Dumitraş, and Radu Marculescu. 2007. Stochastic communication: a new paradigm for fault-tolerant networks-on-chip. VLSI Des. 2007, Article ID 95348, 17 pages.Google Scholar
- Paul Bogdan and Radu Marculescu. 2011. Hitting time analysis for fault-tolerant communication at nanoscale in future multiprocessor platforms. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 30, 8 (Aug. 2011), 1197--1210. Google ScholarDigital Library
- Tung-Chieh Chen, Yao-Wen Chang, and Shyh-Chang Lin. 2008. A new multilevel framework for large-scale interconnection-driven floorplanning. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 27, 2 (Feb. 2008), 286--294. Google ScholarDigital Library
- Yiou Chen, Jianhao Hu, and Xiang Ling. 2009. De Bruijn graph based 3D network on chip architecture design. In Proceedings of the International Conference on Communications, Circuits and Systems (ICCCAS 2009). 986--990. Google ScholarCross Ref
- Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest, and Clifford Stein. 2009. Introduction to Algorithms (3rd ed.). MIT Press.Google Scholar
- William James Dally and Brian Patrick Towles. 2005. Principles and practices of interconnection networks. Morgan Kaufmann.Google Scholar
- Jeffrey A. Davis. 2001. Interconnect limits on gigascale integration (GSI) in the 21st century. In Proc. IEEE 89, 3 (Mar. 2001), 305--324. Google ScholarCross Ref
- Brett Stanley Feero and Partha Pratim Pande. 2005. Networks-on-chip in a three-dimensional environment: A performance evaluation. IEEE Trans. Comput. 58, 1 (Jan. 2005), 32--45. Google ScholarDigital Library
- David Fick. 2009. A highly resilient routing algorithm for fault-tolerant NoCs. In Proceedings of the Design, Automation 8 Test in Europe Conference (DATE). 21--26. Google ScholarCross Ref
- Alberto Ghiribaldi. 2014. A vertically integrated and interoperable multi-vendor synthesis flow for predictable NoC design in nanoscale technologies. In Proceedings of the 19th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC). 337--342. Google ScholarCross Ref
- Mitchell Hayenga, Daniel R. Johnson, and Mikko Lipasti. 2012. Pitfalls of Orion-based simulation. In Proceedings of the 10th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD-10).Google Scholar
- Rickard Holsmarka, Maurizio Palesib, and Shashi Kumara. 2008. Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions. J. Syst. Arch. 54, 3--4, (Mar.-Apr. 2008), 427--440.Google Scholar
- Makoto Imase and Masaki Itoh. 1981. Design to minimize diameter on building-block network. IEEE Trans. Comput. C-30, 6 (Jun. 1981), 439--442. Google ScholarDigital Library
- Makoto Imase and Masaki Itoh. 1983. A design for directed graphs with minimum diameter. IEEE Trans. Comput. C-32, 8 (Aug. 1983), 782--784. Google ScholarDigital Library
- Antoine Jalabert, Srinivasan Murali, Luca Benini, and Giovanni De Micheli. 2004. ×pipesCompiler: A tool for instantiating application specific networks on chip. In Proceedings of the IEEE/ACM Design, Automation, and Test in Europe Conference (DATE). 884--889.Google ScholarCross Ref
- Yuan-Long Jeang, Jer-Min Jou, and Win-Hsien Huang. 2005. A binary tree based methodology for designing an application specific network-on-chip (ASNOC). IEICE Trans. Fundam. Electron.Commun. Comput. Sci. E88-A, 12 (Dec. 2005), 3531--3538.Google ScholarDigital Library
- Yuan-Long Jeang, Tzuu-Shaang Wey, Hung-Yu Wang, Chung-Wei Hung, and Ji-Hong Liu. 2008. An adaptive routing algorithm for mesh-tree architecture in network- on-chip designs. In Proceedings of the 3rd International Conference on Innovative Computing Information and Control. 18--20. Google ScholarDigital Library
- Slavissa Jovanovic, Camel Tanougast, Serge Weber, and Christophe Bobda. 2009. A new deadlock-free fault-tolerant routing algorithm for NoC interconnections. In Proceedings of the 2009 International Conference on Field Programmable Logic and Applications. 326--331. Google ScholarCross Ref
- Andrew B. Kahng, Bin Li, Li-Shiuan Peh, and Kambiz Samadi. 2009. Orion 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In Proceedings of the IEEE/ACM Design, Automation, and Test in Europe Conference (DATE). 423--428.Google ScholarCross Ref
- Woo Joo Kim and Sun Young Hwang. 2008. Design of an area-efficient and low-power NoC architecture using a hybrid network topology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E91-A, 11 (Nov. 2008), 3297--3303.Google ScholarDigital Library
- Katherine Shu-Min Li. 2013. CusNoC: Fast full-chip custom NoC generation. IEEE Trans. VLSI) Syst. 21, 4 (Apr. 2013), 692--705.Google Scholar
- Huai-En Lian, Chien Chen, Je-Wei Chang, Chien-Chung Shen, and Rong-Hong Jan. 2009. Shortest path routing with reliability requirement in delay tolerant networks. In Proceedings of the International Conference on Future Information Networks (ICFIN). 92--297.Google Scholar
- Guoping Liu and Kyungsook Lee. 1993. Optimal routing algorithms for generalized De Bruijn digraphs. In Proceedings of the International Conference on Parallel Processing. 67--174. Google ScholarDigital Library
- Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, and Luca Benini. 2011. Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 30, 1 (Jan. 2011), 124--134. Google ScholarDigital Library
- Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger, and Yatin Hoskote. 2009. Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 28, 1 (Jan. 2009), 3--21. Google ScholarDigital Library
- Hiroki Matsutani. 2013. A case for wireless 3D NoCs for CMPs. In Proceedings of the 18th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC). 23--28. Google ScholarCross Ref
- Nobuaki Miyakawa. 2009. A 3D prototyping chip based on a wafer-level stacking technology. In Proceedings of the 14th IEEE/ACM Asia and South Pacific Design Automation Conference. 416--420. Google ScholarCross Ref
- Srinivasan Murali, Luca Benini, and Giovanni Micheli. 2005. Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. In Proceedings of the 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC). 27--32.Google Scholar
- Srinivasan Murali. 2006. Designing application-specific networks on chips with floorplan information. In Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design. 355--362.Google ScholarDigital Library
- Srinivasan Murali, Ciprian Seiculescu, Luca Benini, and Giovanni De Micheli. 2009. Synthesis of networks on chips for 3D systems on chip. In Proceedings of the 14th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC). 242--247. Google ScholarCross Ref
- Jari Nurmi. 2005. Network-on-chip: A new paradigm for system-on-chip design. In Proceedings of the 2005 International Symposium on System-on-Chip. 2--6. Google ScholarCross Ref
- Dongkook Park, C. Nicopoulos, Jongman Kim, N. Vijaykrishnan, and Chita R. Das. 2006. Exploring fault-tolerant network-on-chip architectures. In Proceedings of the International Conference on Dependable Systems and Networks (DSN’06). 93--104. Google ScholarDigital Library
- Vladimir Pasca, Lorena Anghel, Claudia Rusu, and Mounir Benabdenbi. 2010. Configurable serial fault-tolerant link for communication in 3D integrated systems. In Proceedings of the 16th IEEE International On-Line Testing Symposium. 115--120. Google ScholarDigital Library
- Alessandro Pinto, Luca P. Carloni, and Alberto L. Sangiovanni-Vincentelli. 2009. A methodology for constraint-driven synthesis of on-chip communication. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 28, 3 (Mar. 2009), 364--377. Google ScholarDigital Library
- Amir-Mohammad Rahmani. 2011. Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures. In Proceedings of the IEEE/ACM International Symposium on Networks on Chip (NoCS). 65--72. Google ScholarDigital Library
- Mohammad Reza Nouri Rad, Reza Kourdy, Majid Rahimi Nasab, and Mohammad Poyan. 2010. Improvement the NOC bandwidth and fault tolerant by multipath routing in three-dimensional topologies for multi-media applications. In Proceedings of the 2nd International Conference on Computer and Automation Engineering (ICCAE). 497--501.Google Scholar
- Mehrdad Seyrafi. 2010. A new low cost fault tolerant solution for mesh based NoC. In Proceedings of International Conference on Electronics and Information Engineering (ICEIE). 207--213. Google ScholarCross Ref
- Krishnan Srinivasan, Karam S. Chatha, and Goran Konjevod. 2005. An automated technique for topology and route generation of application specific on-chip interconnection networks. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 231--237. Google ScholarCross Ref
- Krishnan Srinivasan, Karam S. Chatha, and Goran Konjevod. 2006a. Linear-programming-based techniques for synthesis of networks-on-chip architectures. IEEE Trans. VLSI Syst. 14, 4 (Apr. 2006), 407--420. Google ScholarDigital Library
- Krishnan Srinivasan and Karam S. Chatha. 2006b. A methodology for layout aware design and optimization of custom network-on-chip architectures. In Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED’06). 352--357. Google ScholarDigital Library
- B. Swinnen. 2006. 3-D integration by cu-cu thermo-compression bonding of extremely thinned bulk-Si die containing 10μm pitch through-Si vias. In Proceedings of the IEEE International Electron Devices Meeting (IEDM). 1--4.Google Scholar
- Anna W. Topol. 2005. Enabling SOI based assembly technology for three dimensional (3D) integrated circuits (ICs). In Proceedings of the IEEE International Electron Devices Meeting (IEDM). 352--355. Google ScholarCross Ref
- Anna W. Topol. 2006. Three-dimensional integrated circuits. IBM J. Res. Dev. 50, 4/5, (Jul./Sep. 2006), 491--506.Google ScholarCross Ref
- Vijay V. Vazirani. 2003. Approximation Algorithms. Springer. Google ScholarCross Ref
- Yaoyao Ye. 2013. 3D mesh-based optical network-on-chip for multiprocessor system-on-chip. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 32, 4 (Apr. 2013), 584--596. Google ScholarDigital Library
- Pingqiang Zhou, Ping-Hung Yuh, and Sachin S. Sapatnekar. 2010. Application-specific 3D network-on-chip design using simulated allocation. In Proceedings of the 15th IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC). 517--522.Google Scholar
Index Terms
- Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip
Recommendations
Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more ...
Fault-Tolerant Network Interfaces for Networks-on-Chip
As the complexity of designs increases and technology scales down into the deep-submicron domain, the probability of malfunctions and failures in the networks-on-chip (NoCs) components increases. In this work, we focus on the study and evaluation of ...
On the Effects of Process Variation in Network-on-Chip Architectures
The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall ...
Comments