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Reading spin-torque memory with spin-torque sensors
NANOARCH '13: Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale ArchitecturesSpin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate for future on-chip memory, owing to its high-density, zero-leakage and energy efficiency. In a conventional STT-MRAM cache write operations consume larger energy as ...
Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019Existing studies have uncovered that there exist significant Raw Bit Error Rates (RBERs) variations among different layers of 3D flash memories due to manufacture process variation. These RBER variations would cause significantly diversed read latencies ...
WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory
This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM—attributed to PCM SET—...
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