Abstract
GP-SIMD, a novel hybrid general-purpose SIMD architecture, addresses the challenge of data synchronization by in-memory computing, through combining data storage and massive parallel processing. In this article, we explore a resistive implementation of the GP-SIMD architecture. In resistive GP-SIMD, a novel resistive row and column addressable 4F2 crossbar is utilized, replacing the modified CMOS 190F2 SRAM storage previously proposed for GP-SIMD architecture. The use of the resistive crossbar allows scaling the GP-SIMD from few millions to few hundred millions of processing units on a single silicon die. The performance, power consumption and power efficiency of a resistive GP-SIMD are compared with the CMOS version. We find that PiM architectures and, specifically, GP-SIMD benefit more than other many-core architectures from using resistive memory. A framework for in-place arithmetic operation on a single multivalued resistive cell is explored, demonstrating a potential to become a building block for next-generation PiM architectures.
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- Fabien Alibart, Liang Gao, Brian D. Hoskins, and Dmitri B. Strukov. 2012. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23, (Jan. 2012), 075201. DOI:10.1088/0957-4484/23/7/075201Google Scholar
- Fabien Alibart, Timothy Sherwood, and Dmitri B. Strukov. 2011. Hybrid CMOS/nanodevice circuits for high throughput pattern matching applications. In 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE, 279--286. DOI:10.1109/AHS.2011.5963948Google Scholar
- Doug Burger and Todd M. Austin. 1997. The SimpleScalar tool set, version 2.0. ACM SIGARCH Computer Architecture News 25, 3 (June 1997), 13--25. DOI:10.1145/268806.268810 Google ScholarDigital Library
- Yuval Cassuto, Shahar Kvatinsky, and Eitan Yaakobi. Sneak-Path constraints in Memristor crossbar arrays. In 2013 IEEE International Symposium on Information Theory Proceedings (ISIT). IEEE, 156--160. DOI:10.1109/ISIT.2013.6620207Google Scholar
- Meng-Fan Chang, Che-Wei Wu, Chia-Cheng Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, and Yu-Der Chih. 2012. A 0.5 v 4 Mb logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE, 434--436. DOI:10.1109/ISSCC.2012.6177079Google Scholar
- Meng-Fan Chang, Chien-Chen Lin, Albert Lee, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Pei-Ling Tseng, Heng-Yuan Lee, Tzu-Kun Ku, National Chiao Tung University. 2015. A 3T1R non-volatile TCAM using MLC ReRAM with sub-1ns search Time. In IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. (Feb 2015), 318--449.Google Scholar
- Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, and Biji Jacob. 2013. Technology comparison for large last-level caches (L 3 Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA’13). IEEE, 143--154. DOI:10.1109/HPCA.2013.6522314 Google ScholarDigital Library
- Yi-Chou Chen, C. F. Chen, C. T. Chen, J. Y. Yu, S. Wu, S. L. Lung, Rich Liu, and Chih-Yuan Lu. 2003. An access-transistor-Free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device. In IEEE IEDM. IEEE, 37.4.1--37.4.4. DOI:10.1109/IEDM.2003.1269425Google Scholar
- Eric S. Chung, Peter A. Milder, James C. Hoe, and Ken Mai. 2010. Single-chip heterogeneous computing: Does the future include custom logic, FPGAs, and GPGPUs? In 43rd Annual IEEE/ACM International Symposium on Microarchitecture. IEEE, 225--236. DOI:10.1109/MICRO.2010.36 Google ScholarDigital Library
- Timothy Davis and Yifan Hu. 2011. The University of Florida sparse matrix collection. ACM Transactions on Mathematical Software (TOMS) 38, 1 (2011), 1. Google ScholarDigital Library
- Richard Dorrance, Fengbo Ren, and Dejan Marković. 2014. A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-BLAS on FPGAs. In 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, New York, 161--170. DOI:10.1145/2554688.2554785 Google ScholarDigital Library
- Kamran Eshraghian, Kyoung-Rok Cho, Omid Kavehei, Soon-Ku Kang, Derek Abbott, and Sung-Mo Steve Kang. 2011. Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines. IEEE Trans. VLSI Systems, 19, 8 (July 2011), 1407--1417. DOI:10.1109/TVLSI.2010.2049867 Google ScholarDigital Library
- Seungbum Hong, Orlando Auciello, and Dirk J. Wouters. 2014. Emerging Non-Volatile Memories. Springer-Verlag, New York.Google Scholar
- Mark Horowitz. 2014. 1.1 Computing's energy problem (and what we can do about it). In Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE, 10--14. DOI:10.1109/ISSCC.2014.6757323Google ScholarCross Ref
- I. T. R. S. Roadmap. Retrieved from http://www.itrs.net/Google Scholar
- Shoaib Kamil, Cy Chan, Leonid Oliker, John Shalf, and Samuel Williams. 2010. An auto-tuning framework for parallel Multicore stencil computations. In IEEE International Symposium on Parallel & Distributed Processing. IEEE, 1--12. DOI:10.1109/IPDPS.2010.5470421Google ScholarCross Ref
- Akifumi Kawahara, Ryotaro Azuma, Yasuhiro Ikeda, Kunihiro Kawai, Yoshikazu Katoh, Yoshikazu Hayakawa, Keita Tsuji, Shinichi Yoneda, Atsushi. Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, and Kunioshi Aono. 2013. An 8 Mb Multi-layered cross-point ReRAM Macro with 443 MB/s write throughput. IEEE J. Solid-State Circuits 48, 1 (Dec. 2012), 178--185. DOI:10.1109/JSSC.2012.2215121Google ScholarCross Ref
- Jakub Kurzak, David A. Bader, and Jack Dongarra. 2010. Scientific Computing with Multicore and Accelerators. CRC Press, Inc., Boca Raton, FL. Google ScholarDigital Library
- Shahar Kvatinsky, Eby G. Friedman, Avinoam. Kolodny, and Uri C. Weiser. 2013. TEAM: threshold adaptive Memristor model. IEEE Trans. Circuits Syst. I 60, 1 (Jan. 2013), 211--221. DOI:10.1109/TCSI.2012.2215714Google Scholar
- Shahar Kvatinsky, Keren Talisveyberg, Dmitry Fliter, Avinoam Kolodny, Uri C. Weiser, and Eby G. Friedman. 2012. Models of Memristors for SPICE simulations. In IEEE Convention of Electrical and Electronics Engineers in Israel. IEEE, 1--5.Google Scholar
- Shahar Kvatinsky, Nimrod Wald, Guy Satat, Avinoam Kolodny, Uri C. Weiser, and Eby G. Friedman. 2012b. MRL - Memristor Ratioed logic. In 13th International Workshop on Cellular Nanoscale Networks and Their Applications. IEEE, 29--31. DOI:10.1109/CNNA.2012.6331426Google Scholar
- R. Lauwereins. 2015. New memory technologies and their impact on computer architectures. HiPeac’15 keynote.Google Scholar
- Colin Yu Lin, Ngai Wong, and Hayden Kwok-Hay So. 2013. Design space exploration for sparse matrix-matrix multiplication on FPGAs. Int. J. Circ. Theor. Appl. 41, 2 (Feb. 2013), 205--219. DOI:10.1002/cta.796.Google ScholarCross Ref
- T.-Y. Liu, Tian Hong Yan, R. Scheuerlein, Yingchang Chen, K. K. Lee, and G. Balakrishnan. 2013. A 130.7 mm2 2-layer 32 Gb ReRAM memory device in 24 nm technology. In IEEE International Solid-State Circuits Conference, 49, 1 (Feb. 2013), 210--211. DOI:10.1109/JSSC.2013.2280296Google Scholar
- Xing Liu, Mikhail Smelyanskiy, Edmond Chow, and Pradeep Dubey. 2013b. Efficient sparse matrix-vector multiplication on x86-based many-core processors. In International Conference on Supercomputing. ACM, New York, 273--282. DOI:10.1145/2464996.2465013 Google ScholarDigital Library
- Amir Morad, Leonid Yavits, and Ran Ginosar. 2014. Efficient dense and sparse Matrix multiplication on GP-SIMD. In Power and Timing Modeling, Optimization and Simulation. IEEE, 1--8. DOI:10.1109/PATMOS.2014.6951895Google Scholar
- Amir Morad, Leonid Yavits, and Ran Ginosar. 2015. GP-SIMD processing-in-memory. ACM Trans. Archit. Code Optim. 11, 4 (Jan. 2015), Article 53. DOI:10.1145/2686875 Google ScholarDigital Library
- J. Nickel. 2011. Memristor materials engineering: from flash replacement towards a universal memory. In Proceedings of the IEEE International Electron Devices Meeting. December 2011.Google Scholar
- Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, and Yuan Xie. 2012. Design trade-offs for high density cross-point resistive memory. In 2012 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’12). ACM, New York, 209--214. DOI:10.1145/2333660.2333712 Google ScholarDigital Library
- Elaine Ou and S. Simon Wong. 2011. Array architecture for a nonvolatile 3-dimensional cross-point resistance-change memory. IEEE J. Solid-State Circuits 46, 9 (Aug. 2011), 2158--2170. DOI:10.1109/JSSC.2011.2148430Google ScholarCross Ref
- Rahul Patel, Shahar Kvatinsky, Eby G. Friedman, and Avinoam Kolodny. 2014. Multistate register based on resistive RAM. IEEE Trans. VLSI Syst. 23, 9 (Aug. 2015), 1750--1759. DOI:10.1109/TVLSI.2014.2347926Google ScholarDigital Library
- Ravi Patel and Eby G. Friedman. 2012. Arithmetic encoding for memristive multi-bit storage. In IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC’12). IEEE, 99--104. DOI:10.1109/VLSI-SoC.2012.7332084Google Scholar
- Erik Saule, Kamer Kaya, and Ümit V. Çatalyürek. 2014. Performance evaluation of sparse Matrix multiplication kernels on Intel Xeon Phi. arXiv preprint arXiv:1302.1078.Google Scholar
- Shyh-Shyuan Shu, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Tai-Yuan Wu, Frederick T. Chen, Keng-Li Su, Ming-Jer Kao, Kuo-Hsing Cheng, and Ming-Jinn Tsai. 2009. A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme. In Symposium on VLSI circuits. IEEE, 82, 83.Google Scholar
- Jonathan Thatcher, Tom Coughlin, Jim Handy, and Neal Ekker. 2009. NAND flash solid state storage for the Enterprise, an in-depth look at reliability. In Solid State Storage Initiative (SSSI) of the Storage Network Industry Association (SNIA’09).Google Scholar
- Antonio C. Torrezan, John Paul Strachan, Gilberto Medeiros-Ribeiro, and R. Stanley Williams. 2011. Sub-nanosecond switching of a tantalum oxide memristor. Nanotechnology 22, 48 (2011), 485203.Google ScholarCross Ref
- Samual Williams, Leonid Oliker, Richard Vuduc, John Shalf, Katherine Yelick, and James Demmel. 2009. Optimization of sparse matrix--vector multiplication on emerging multicore platforms. Parallel Comput. 35, 3 (March 2009), 178--194. DOI:10.1016/j.parco.2008.12.006 Google ScholarDigital Library
- H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, and Ming-Jinn Tsai. 2012. Metal--oxide RRAM. Proc. IEEE 100, 6 (June 2012), 1951,1970. DOI:10.1109/JPROC.2012.2190369Google Scholar
- Ming-Chi Wu, Yi-Wei Lin, Wen-Yueh Jang, Chen-Hsi Lin, and Tseung-Yuen Tseng. 2011. Low-Power and highly reliable multilevel operation in ZrO2 1T1R RRAM. IEEE Electron. Dev. Lett., 32, 8 (July 2011), 1026--1028. DOI:10.1109/LED.2011.2157454Google ScholarCross Ref
- Cong Xu, Xiangyu Dong, Norman P. Jouppi, and Yuan Xie. 2011. Design implications of Memristor-Based RRAM cross-point structures. In Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1--6. DOI:10.1109/DATE.2011.5763125Google Scholar
- Leonid Yavits, Amir Morad, and Ran Ginosar. 2014a. Computer architecture with associative processor replacing last-level cache and SIMD accelerator. IEEE Trans. Comput. 64, 2 (Jan. 2015), 368--381. DOI:10.1109/TC.2013.220.Google ScholarDigital Library
- Leonid Yavits, Amir Morad, and Ran Ginosar. 2014b. The effect of communication and synchronization on Amdahl's law in multicore systems. Parallel Computing 40, 1 (Jan. 2014), 1--16. DOI:10.1016/j.parco.2013.11.001. Google ScholarDigital Library
- Leonid Yavits, Shahar kvatinsky, Amir Morad, and Ran Ginosar. 2014. Resistive associative processor. IEEE Comput. Arch. Lett. PP, 99 (Nov. 2014), 1. DOI:10.1109/LCA.2014.2374597.Google ScholarDigital Library
- Mohsen Zangeneh and Akanksha Joshi. 2014. Design and optimization of nonvolatile Multibit 1T1R resistive RAM. IEEE Trans. Very Large Scale Integrat (VLSI) Syst. 22, 8 (July 2014), 1815--1828. DOI:10.1109/TVLSI.2013.2277715Google Scholar
Index Terms
- Resistive GP-SIMD Processing-In-Memory
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