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LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems

Published:30 September 2013Publication History
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Abstract

It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this article, we introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGA-based MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixed-sized multidimensional arrays, structs, global variables, and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software codesign space by varying the amount of a program that runs in software versus hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of high-level synthesis topics.

References

  1. Aldham, M., Anderson, J., Brown, S., and Canis, A. 2011. Low-cost harware profiling of run-time and energy in FPGA embedded processors. In Proceedings of the IEEE International Conference on Application-specific Systems, Architecture and Processors (ASAP). 61--68. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Altera, Corp. 2009. Nios II C2H Compiler User Guide. Altera, Corp., San Jose, CA.Google ScholarGoogle Scholar
  3. Altera, Corp. 2010. Avalon interface specification. Altera, Corp., San Jose, CA.Google ScholarGoogle Scholar
  4. Altera, Corp. 2011. Stratix IV FPGA family data sheet. Altera, Corp., San Jose, CA.Google ScholarGoogle Scholar
  5. AutoESL. 2011. AutoESL Design Technologies, Inc. http://www.autoesl.com.Google ScholarGoogle Scholar
  6. Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the International Workshop on Field Programmable Logic and Applications. 213--222. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Cadence. 2010. Cadence C-to-Silicon compiler. http://www.cadence.com/products/sd/silicon.Google ScholarGoogle Scholar
  8. Canis, A., Choi, J., Aldham, M., Zhang, V., Kammoona, A., Anderson, J., Brown, S., and Czajkowski, T. 2011. LegUp: High-level synthesis for FPGA-based processor/accelerator systems. In Proceedings of the ACM International Symposium on Field Programmable Gate Arrays. 33--36. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. CebaTech. 2010. CebaTech The software to silicon company. http://www.cebatech.com.Google ScholarGoogle Scholar
  10. Chen, D. and Cong, J. 2004. Register binding and port assignment for multiplexer optimization. In Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference. 68--73. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Cong, J., Fan, Y., Han, G., Jiang, W., and Zhang, Z. 2006. Platform-based behavior-level and system-level synthesis. In Proceedings of the IEEE International System-on-Chip Conference. 199--202.Google ScholarGoogle Scholar
  12. Cong, J. and Zhang, Z. 2006. An efficient and versatile scheduling algorithm based on SDC formulation. In Proceedings of the IEEE/ACM Design Automation Conference. 433--438. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Cong, J. and Zou, Y. 2009. FPGA-based hardware acceleration of lithographic aerial image simulation. ACM Trans. Reconfig. Technol. Syst. 2, 3, 1--29. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Coussy, P., Gajski, D., Meredith, M., and Takach, A. 2009. An introduction to high-level synthesis. IEEE Des. Test Comput. 26, 4, 8--17. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Coussy, P., Lhairech-Lebreton, G., Heller, D., and Martin, E. 2010. GAUT -- A free and open source high-level synthesis tool. In Proceedings of the IEEE Design Automation and Test in Europe. University Booth.Google ScholarGoogle Scholar
  16. De2. 2010. DE2 development and education board. DE2, Altera Corp, San Jose, CA.Google ScholarGoogle Scholar
  17. Forte. 2010. Forte design systems the high level design company. http://www.forteds.com/products/cynthesizer.asp.Google ScholarGoogle Scholar
  18. Gajski, D., Dutt, N. D., Wu, A. C.-H., and Lin, S. Y.-L. 1992. High-Level Synthesis - Introduction to Chip and System Design. Kluwer Academic Publishers. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Hara, Y., Tomiyama, H., Honda, S., and Takada, H. 2009. Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis. J. Inf. Process. 17, 242--254.Google ScholarGoogle ScholarCross RefCross Ref
  20. Henkel, J. 2003. Closing the SoC design gap. IEEE Comput. 36, 119--121. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Huang, C. Y., Che, Y. S., Lin, Y. L., and Hsu, Y. C. 1990. Data path allocation based on bipartite weighted matching. In Proceedings of the ACM/IEEE Design Automation Conference. 499--504. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Huang, S., Hormati, A., Bacon, D., and Rabbah, R. 2008. Liquid metal: Object-oriented programming across the hardware/software boundary. In Proceedings of the ACM European Conference on Object-Oriented Programming. 76--103. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Impulse. 2010. Impulse CoDeveloper -- Impulse accelerated technologies. http://www.impulseaccelerated.com.Google ScholarGoogle Scholar
  24. Kuhn, H. 2010. The Hungarian method for the assignment problem. In 50 Years of Integer Programming 1958--2008, Springer, 29--47.Google ScholarGoogle Scholar
  25. LLVM. 2010. The LLVM compiler infrastructure project. http://www.llvm.org.Google ScholarGoogle Scholar
  26. Lp. 2011. Lp solve linear programming solver. http://lpsolve.sourceforge.net/5.5/.Google ScholarGoogle Scholar
  27. Luu, J., Redmond, K., Lo, W., Chow, P., Lilge, L., and Rose, J. 2009. FPGA-based monte carlo computation of light absorption for photodynamic cancer therapy. In Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines. 157--164. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Mentor Graphics. 2010. http://www.mentor.com/products/esl/high-level_synthesis.Google ScholarGoogle Scholar
  29. Mishchenko, A., Chatterjee, S., and Brayton, R. 2006. DAG-aware AIG rewriting: A fresh look at combinational logic synthesis. In Proceedings of the IEEE/ACM Design Automation Conference. 532--536. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. PLB. 2011. Xilinx Inc. processor local bus. http://www.xilinx.com/support/documentation/ip_documentation/plb_v46.pdf.Google ScholarGoogle Scholar
  31. Pothineni, N., Brisk, P., Ienne, P., Kumar, A., and Paul, K. 2010. A high-level synthesis flow for custom instruction set extensions for application-specific processors. In Proceedings of the ACM/IEEE Asia and South Pacific Design Automation Conference. 707--712. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Pozzi, L., Atasu, K., and Ienne, P. 2006. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 25, 7, 1209--1229. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Putnam, A., Bennett, D., Dellinger, E., Mason, J., Sundararajan, P., and Eggers, S. 2008. CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures. In Proceedings of the IEEE International Conference on Field Programmable Logic and Applications. 173--178.Google ScholarGoogle Scholar
  34. Stitt, G. and Vahid, F. 2007. Binary synthesis. ACM Trans. Des. Autom. Electron. Syst. 12, 3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Sun, F., Raghunathan, A., Ravi, S., and Jha, N. 2004. Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 23, 7, 216--228. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Tripp, J., Gokhale, M., and Peterson, K. 2007. Trident: From high-level language to hardware circuitry. IEEE Comput. 40, 3, 28--37. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. United States Bureau of Labor Statistics. 2010. Occupational Outlook Handbook 2010--2011 Edition. United States Bureau of Labor Statistics.Google ScholarGoogle Scholar
  38. University of Cambridge. 2010. The tiger MIPS processor. http://www.cl.cam.ac.uk/teaching/0910/ECAD+Arch/mips.html.Google ScholarGoogle Scholar
  39. Vahid, F., Stitt, G., and Lysecky, R. 2008. Warp processing: Dynamic translation of binaries to FPGA circuits. IEEE Comput. 41, 7, 40--46. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. Villarreal, J., Park, A., Najjar, W., and Halstead, R. 2010. Designing modular hardware accelerators in C with ROCCC 2.0. In Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines. 127--134. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. VTR. 2011. VTR -- the Verilog-to-routing project for FPGAs. http://www.eecg.toronto.edu/vtr/.Google ScholarGoogle Scholar
  42. Wayne Marx, V. A. 2008. FPGAs are everywhere. In design, test & control. RTC Mag (7/25/08).Google ScholarGoogle Scholar
  43. Xilinx. 2011. CoreConnect, Xilinx, Inc. http://www.xilinx.com/support/documentation/ipembedprocesscoreconnect.htm.Google ScholarGoogle Scholar
  44. Y Explorations (XYI). 2010. eXCite C to RTL Behavioral Synthesis 4.1(a). Y Explorations (XYI), San Jose, CA.Google ScholarGoogle Scholar

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    • Published in

      cover image ACM Transactions on Embedded Computing Systems
      ACM Transactions on Embedded Computing Systems  Volume 13, Issue 2
      Special issue on application-specific processors
      September 2013
      254 pages
      ISSN:1539-9087
      EISSN:1558-3465
      DOI:10.1145/2514641
      Issue’s Table of Contents

      Copyright © 2013 ACM

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      Publication History

      • Published: 30 September 2013
      • Accepted: 1 May 2012
      • Revised: 1 February 2012
      • Received: 1 February 2011
      Published in tecs Volume 13, Issue 2

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