G. A. Constantinides
P. Y. K. Cheung
Abstract
This paper describes a synthesis technique for automating the design of linear Digital Signal Processing (DSP) systems such as digital filters. The proposed methodology makes optimized use of saturation arithmetic to produce a small design implemented directly in hardware. An analytical technique is proposed to estimate the saturation error resulting from a particular implementation, and an optimization procedure is introduced to aim for the smallest implementation satisfying user-specified bounds on saturation and roundoff error. Results are presented illustrating significant speedup and area reduction compared with standard DSP design techniques: up to 22% improvement in area and 28% improvement in speed have been obtained on Field Programmable Gate Array (FPGA) implementations.
- Altera Corporation. 1998. Altera Databook. San Jose: Altera Corporation.Google Scholar
- Benedetti, A. and Perona, P. 2000. Bit-width optimization for configurable DSPs by multi-interval analysis. In Proceedings of the 34th Asilomar Conference on Signals, Systems and Computers.Google Scholar
- Chung, K.-L. 1974. A Course in Probability Theory. Academic Press, New York.Google Scholar
- Cmar, R., Rijnders, L., Schaumont, P., Vernalde, S., and Bolsens, I. 1999. A methodology and design environment for DSP ASIC fixed point refinement. In Proceedings on Design Automation and Test in Europe, München. Google Scholar
- Constantinides, G. A. 2001. High Level Synthesis and Word Length Optimization of Digital Signal Processing Systems. Ph.D. thesis, University of London.Google Scholar
- Constantinides, G. A. 2003. Perturbation analysis for word-length optimization. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. Google Scholar
- Constantinides, G. A., Cheung, P. Y. K., and Luk, W. 2001. The multiple wordlength paradigm. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines Rohnert Park, CA, April--May. Google Scholar
- DeMicheli, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York. Google Scholar
- Ercegovac, M., Kirovski, D., and Potkonjak, M. 1999. Low-power behavioural synthesis optimization using multiple precision arithmetic. In Proceedings of the 37th Design Automation Conference. Google Scholar
- FREETEL. 1993. Esprit project 6166: FREETEL database.Google Scholar
- Johnson, K. K. and Sandberg, I. W. 1995. A separation theorem for finite precision digital filters. IEEE Trans. Circuits and Syst. I 42, 9 (September), 541--545.Google Scholar
- Kim, S., Kum, K., and Sung, W. 1998. Fixed-point optimization utility for C and C++ based digital signal processing programs. IEEE Trans. Circuits Syst. II 45, 11 (November), 1455--1464.Google Scholar
- Kum, K.-I. and Sung, W. 2001. Combined word-length optimization and high-level synthesis of digital signal processing systems. IEEE Trans. Comput. Aided Design 20, 8 (August), 921--930. Google Scholar
- Leong, M. P., Yeung, M. Y., Fu, C. W., Heng, P. A., and Leong, P. H. W. 1999. Automatic floating to fixed point translation and its application to post-rendering 3D warping. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 240--248. Google Scholar
- Liu, B. 1971. Effect of finite word length on the accuracy of digital filters---a review. IEEE Trans. Circuit Theory CT-18, 6, 670--677.Google Scholar
- Mitra, S. K. 1998. Digital Signal Processing. McGraw-Hill, New York. Google Scholar
- Oppenheim, A. V. and Weinstein, C. J. 1972. Effects of finite register length in digital filtering and the fast fourier transform. IEEE Proceedings 60, 8, 957--976.Google Scholar
- Stephenson, M., Babb, J., and Amarasinghe, S. 2000. Bitwidth analysis with application to silicon compilation. In Proceedings of the SIGPLAN Programming Language Design and Implementation, Vancouver, British Columbia, (June). Google Scholar
- Willems, M., Bürsgens, V., Keding, H., Grötker, T., and Meyer, M. 1997. System-level fixed-point design based on an interpolative approach. In Proceedings of the 34th Design Automation Conference (June). 293--298. Google Scholar
Index Terms
- Synthesis of saturation arithmetic architectures
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