Mark Bohr
- 1 Agnello, P., Newman, T., Crabbe, E., Subbanna, S., Ganin, E., Liebmann, L., Comfort, J., and Sunderland, D. Phase edge lithography for sub-0.1 btm electrical channel length in a 200mm full CMOS process. In Tech. Dig. of the Symposium on VLSI Technology (Kyoto, June 6-8, 1995), IEEE Press, Piscataway, N.J., pp. 79-80.Google Scholar
- 2 Asai, S., and Wada, Y. Technology challenges for integration near and below 0.1btm. Proc. IEEE 85, 4 (April 1997), 505-520.Google ScholarCross Ref
- 3 Bohr, M. Interconnect scaling--The real limiter to high-performance ULSI. In Tech. Dig. of the International Electron Devices Meeting (Washington, D.C., Dec. 10-13, 1995), IEEE Press, Piscataway, N.J., pp. 241-244.Google ScholarCross Ref
- 4 Bohr, M., Ahmed, S., Brigham, L., Chau, R., Gasser, R., Green, R., Hargrove, W., Lee, E., Natter, R., Thompson, S., Weldon, K., and Yang, S. A high-performance 0.35btm logic technology for 3.3V and 2.5V operation. In Tech. Dig. of the International Electron Devices Meeting (San Francisco, Dec. 11-14, 1994), IEEE Press, Piscataway, N.J., pp. 273-276.Google Scholar
- 5 Bohr, M., Ahmed, S., Ahmed, S., Bost, M., Ghani, T., Greason, J., Hainsey, R., Jan, C., Packan, P., Sivakumar, S., Thompson, S., Tsai, J., and Yang, S. A high-performance 0.25 btm logic technology optimized for 1.8V operation. In Tech. Dig. of the International Electron Devices Meeting (San Francisco, Dec. 8-11, 1996), IEEE Press, Piscataway, N.J., pp. 847-850.Google ScholarCross Ref
- 6 Dennard, R., Gaensslen, F., Yu, H., Rideout, V., Bassous, E., and LeBlanc, A. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE ft. Solid State Circuits SC-9, 5 (Oct. 1974), 256-268.Google ScholarCross Ref
- 7 Taur, Y., Buchanan, D., Chen, W., Frank, D., Ismail, K., Lo, S., Sai- Halasz, G., Viswanathan, R., Wann, H., Wind, S., and Wong, H,. CMOS scaling into the nanometer range. Proc. IEEE 85, 4 (April 1997), 486-504.Google Scholar
Index Terms
- Silicon trends and limits for advanced microprocessors
Recommendations
Scaling silicon MOS devices to their limits
Special issue on nanotechnologyThe scaling of silicon CMOS (Complementary Metal-Oxide-Semiconductor) devices to 100 nm channel lengths offers significant potential for high speed circuit performance gains at low levels of power consumption. Continued miniaturization beyond 100 nm ...
Trends of Key Advanced Device Technologies
ARVLSI '97: Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)Silicon CMOS technology has followed Moore's law over the past two decodes. It is still on the predicted curve, and it appears that the trend will continue into the next decade. The SIA roadmap published by Sematech in 1994 predicted the progress of ...
Comments