- Authors:
- Grant McFarland,
- Michael J. Flynn
The fundamental electrical limits of MOSFETs are discussed and modeled to predict the scaling limits of digital bulk CMOS circuits. Limits discussed include subthreshold currents, time dependent dielectric breakdown (TDDB), hot electron effects, and drain induced barrier lowering (DIBL). This paper predicts the scaling of bulk CMOS MOSFETs to reach its limits at drawn dimensions of approximately 0.1um. These electrical limits are used to find scaling factors for SPICE Level 3 model parameters, and a scalable Level 3 device model is presented. Current trends in scaling interconnects are also discussed.
Cited By
Ma Y, Liu Y, Kursun E, Reinman G and Cong J (2008). Investigating the effects of fine-grain three-dimensional integration on microarchitecture design, ACM Journal on Emerging Technologies in Computing Systems (JETC), 4:4, (1-30), Online publication date: 1-Oct-2008.- Balasubramonian R, Albonesi D, Buyuktosunoglu A and Dwarkadas S Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, (245-257)
- Reinman G, Austin T and Calder B A scalable front-end architecture for fast instruction delivery Proceedings of the 26th annual international symposium on Computer architecture, (234-245)
- Reinman G, Austin T and Calder B (1999). A scalable front-end architecture for fast instruction delivery, ACM SIGARCH Computer Architecture News, 27:2, (234-245), Online publication date: 1-May-1999.
- Al-Twaijry H and Flynn M (1998). Technology Scaling Effects on Multipliers, IEEE Transactions on Computers, 47:11, (1201-1215), Online publication date: 1-Nov-1998.
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