ABSTRACT
Energy efficiency of the underlying communication framework plays a major role in the performance of multicore systems. NoCs with buffer-less routing are gaining popularity due to simplicity in the router design, low power consumption, and load balancing capacity. With minimal number of buffers, deflection routers evenly distribute the traffic across links. In this paper, we propose an adaptive deflection router, DeBAR, that uses a minimal set of central buffers to accommodate a fraction of mis-routed flits. DeBAR incorporates a hybrid flit ejection mechanism that gives the effect of dual ejection with a single ejection port, an innovative adaptive routing algorithm, and a selective flit buffering based on flit marking. Our proposed router design reduces the average flit latency and the deflection rate, and improves the throughput with respect to the existing minimally buffered deflection routers without any change in the critical path.
- C. Fallin et al., "CHIPPER: A low complexity bufferless deflection router," in HPCA, 2011, pp. 144--155. Google ScholarDigital Library
- W. Dally, "Virtual-channel flow control," IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194--205, 1992. Google ScholarDigital Library
- W. Dally and B. Towles, Principles and Practices of Interconnection Networks. USA: Morgan Kaufmann Publishers Inc., 2003. Google ScholarDigital Library
- Y. Hoskote et al., "A 5-GHz mesh interconnect for a teraflops processor," IEEE Micro, vol. 27, no. 5, pp. 51--61, 2007. Google ScholarDigital Library
- M. B. Taylor et al., "Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams," in ISCA, 2004. Google ScholarDigital Library
- "SPEC2006 CPU benchmark suite," http://www.spec.org.Google Scholar
- C. Fallin et al., "MinBD: Minimally-buffered deflection routing for energy-efficient interconnect," in NOCS, 2012, pp. 1--10. Google ScholarDigital Library
- T. Moscibroda and O. Mutlu, "A case for bufferless routing in on-chip networks," in ISCA, 2009, pp. 196--207. Google ScholarDigital Library
- M. Hayenga et al., "SCARAB: A single cycle adaptive routing and bufferless network," in MICRO, 2009, pp. 244--254. Google ScholarDigital Library
- C. Gomez et al., "An efficient switching technique for NoCs with reduced buffer requirements," in ICPADS, 2008, pp. 713--720. Google ScholarDigital Library
- E. Nilsson et al., "Load distribution with the proximity congestion awareness in a network-on-chip," in DATE, 2003, pp. 1126--1127. Google ScholarDigital Library
- S. A. R. Jafri et al., "Adaptive flow control for robust performance and energy," in MICRO, 2010, pp. 433--444. Google ScholarDigital Library
- G. Kim et al., "Flexibuffer: Reducing leakage power in on-chip network routers," in DAC, 2011, pp. 936--941. Google ScholarDigital Library
- G. Oxman et al., "Streamlined network-on-chip for multicore embedded architectures," in ARCS, 2012, pp. 238--249. Google ScholarDigital Library
- G. Nychis et al., "Next generation on-chip networks: What kind of congestion control do we need?" in Hotnets'10, 2010, pp. 1--6. Google ScholarDigital Library
- Z. Lu et al., "Evaluation of on-chip networks using deflection routing," in GLSVLSI'06, 2006, pp. 296--301. Google ScholarDigital Library
- R. Ubal et al., "Multi2sim: A simulation framework to evaluate multicore-multithreaded processors," in SBAC-PAD, 2007, pp. 62--68.Google Scholar
- A. B. Kahng et al., "Orion 2.0: A fast and accurate NoC power and area model for early stage design space exploration." in DATE, 2009, pp. 423--429. Google ScholarDigital Library
- W. Zhao and Y. Cao, "Predictive technology model for nano-CMOS design exploration," ACM Journal on Emerging Technologies in Computing Systems, vol. 3, pp. 1--17, 2007. Google ScholarDigital Library
Index Terms
- DeBAR: deflection based adaptive router with minimal buffering
Recommendations
CNoC: High-Radix Clos Network-on-Chip
Many high-radix network-on-chip (NoC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe high-radix Clos network-on-chip (CNoC) is the most promising with its low ...
A High-Throughput Distributed Shared-Buffer NoC Router
Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or ...
Comments