Browse Theses

Routers form the backbone of the Internet; their kernel, structure, and configuration (scheduler) of the backplane (or switching fabrics) dominate the routers' performance, scalability, reliability and cost. As higher performance is required with the rapid development of the network applications, router's architecture has also evolved from the shared backplane to switched backplane, which mainly uses the indirect interconnection networks.

The indirect interconnection networks include crossbar, MIN (multistage interconnection networks) and some other irregular topologies. At present, most of today's routers and switches are implemented on single crossbar with symmetric buffer architecture. In the first part of this dissertation, we introduce novel asymmetric buffer architecture for the crossbar in which a new port and a local shared bus are added. We then evaluate its performance and simulate under different bus arbitration and buffer management algorithms. Our studies indicate that we can get great improvement for the throughput and low drop rate. Thus we could save a lot of expensive link bandwidth and decrease the probability of congestion for the network.

Single crossbar complexity increases at O(N 2 ) in terms of crosspoint number, which become unacceptable for scalability as the port number (N) increases. A delta class self-routing MIN with complexity of O(N×log ₂N) has been widely used in the ATM switches. But the reduction of crosspoint number results in considerable internal blocking. A number of scalable methods have been proposed to solve this problem. One of them uses more stages with recirculation architecture to reroute the deflected packets, which greatly increase the latency. In the second part of this dissertation, we propose an interleaved multistage switching fabrics architecture and assess its throughput with an analytical model and simulations. We compare this novel scheme with some previous parallel architectures and show its benefits. From extensive simulations under different traffic patterns and fault models, our interleaved architecture achieves better performance than its counterpart of single panel fabric. Our interleaved scheme achieves speedups (over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns, respectively at maximum load ( p =1). Moreover, the interleaved fabrics show great tolerance against internal hardware failures.