Xin An
ABSTRACT
This paper presents an abstract multi-clock oriented reasoning for the rapid prototyping of embedded applications executed on multiprocessor systems-on-chip (MPSoCs). The scheduling of applications on execution platforms composed of processors operating at various frequencies is described and analyzed with clocks. As in the static scheduling of synchronous dataflows (SDFs), requirements for admissible schedules are investigated, which come not only from expected application behavior, but also from execution platform. An algorithm is proposed to construct admissible schedules respecting identified requirements. It is then adapted to synthesize admissible schedules for adaptive system behaviors. The modeling, analysis and algorithms presented in this paper have been implemented in a prototype tool named CLASSY (standing for CLock AnalySis SYstem).
- The SoClib Project, 2011. http://www.soclib.fr.Google Scholar
- Xin An, Sarra Boumedien, Abdoulaye Gamatié, and Eric Rutten. CLASSY: a Clock Analysis System for Rapid Prototyping of Embedded Applications on MPSoCs. Rapport de recherche RR-7918, INRIA, March 2012. http://hal.inria.fr/hal-00683822.Google Scholar
- A. Benveniste, P. Caspi, S. A. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone. The synchronous languages 12 years later. Proceedings of the IEEE, 91(1): 64--83, jan 2003.Google ScholarCross Ref
- Abdoulaye Gamatié. Design of Streaming Applications on MPSoCs using Abstract Clocks. In Design, Automation and Test in Europe Conference (DATE'2012), Dresden, Germany, 2012.Google ScholarCross Ref
- A. H. Ghamarian, M. C. W. Geilen, S. Stuijk, T. Basten, A. J. M. Moonen, M. J. G. Bekooij, B. D. Theelen, and M. R. Mousavi. Throughput analysis of synchronous data flow graphs. In In Proc. of ACSD'06, IEEE, pages 25--34, 2006. Google ScholarDigital Library
- Edward A. Lee and Alberto Sangiovanni-vincentelli. A framework for comparing models of computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17: 1217--1229, 1998. Google ScholarDigital Library
- Edward Ashford Lee and David G. Messerschmitt. Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans. Comput., 36: 24--35, January 1987. Google ScholarDigital Library
- Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Carlo Galuzzi, and Koen Bertels. System-level runtime mapping exploration of reconfigurable architectures. In Reconfigurable Architecture Workshop(RAW'09), May 2009. Google ScholarDigital Library
- S. Sriram and S. S. Bhattacharyya. Embedded multiprocessors: Scheduling and synchronization. CRC Press, 2000. Google ScholarDigital Library
- Bruno Virlet, Xing Zhou, Jean Pierre Giacalone, Bob Kuhn, Maria J. Garzaran, and David Padua. Scheduling of stream-based real-time applications for heterogeneous systems. In Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems, LCTES '11, pages 1--10, New York, NY, USA, 2011. ACM. Google ScholarDigital Library
- R. A. Walker and S. Chaudhuri. Introduction to the scheduling problem. Design Test of Computers, IEEE, 12(2): 60 --69, summer 1995. Google ScholarDigital Library
- Jun Zhu, Ingo Sander, and Axel Jantsch. Energy efficient streaming applications with guaranteed throughput on mpsocs. In Proceedings of the 8th ACM international conference on Embedded software, EMSOFT'08, pages 119--128, 2008. Google ScholarDigital Library
Index Terms
- CLASSY: a clock analysis system for rapid prototyping of embedded applications on MPSoCs
Recommendations
Abstract Clocks for the DSE of Data-Intensive Applications on MPSoCs
ISPA '12: Proceedings of the 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with ApplicationsThis paper presents an approach advocating abstract clocks to represent data-intensive applications executed on multiprocessor systems-on-chip (MPSoCs) for facilitating the exploration of large design spaces. By using abstract clocks, the advocated ...
Which On-Chip Interconnection Network for 16-core MPSoCs?
CISIS '10: Proceedings of the 2010 International Conference on Complex, Intelligent and Software Intensive SystemsOn-chip interconnection networks (OCINs) in many-core systems are key to the system’s performance scalability. OCIN design constraints are governed by power, cost, latency, ease of routing, as well as others. As chips with 16 cores are around the corner,...
Hardware support in a middleware for distributed and real-time embedded applications
SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems designOne of the main challenges in the development of tools and methodologies for a multiprocessor real-time embedded system is to reuse already developed software, but at the same time obtaining low memory footprint, low energy consumption, and minimal area,...
Comments