A high speed and leakage-tolerant domino logic for high fan-in gates

ABSTRACT

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in and high-speed applications in ultra deep submicron technologies. The proposed circuit employs a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. According to simulations in a predictive 70nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention between keeper transistor and NMOS evaluation transistors at the beginning of evaluation phase. This results in less power dissipation for the proposed technique.

References

1. K. Roy, et. al., "Leakage tolerant mechanisms and leakage reduction techniques in deep-submicron CMOS circuits," Proceeding of the IEEE, vol. 91, pp.305--327, Feb. 2003.
2. Berkeley Predictive Technology Model. Univ. Berkeley, Berkeley, CA. {online}. Available: http://www-devices.eecs.berkeley.edu/~ptm
3. J. Kao, "Dual Threshold Voltage Domino Logic," in proc. Eur: Solid State Circuit Conf., 1999,pp.118--121.
4. V. kursun, E. Friedman, "Node voltage dependent subthreshold leakage current characteristics of dynamic circuits," IEEE Computer and Society Systems, 2004.
5. B. Chatterjee, et al, "Leakage control techniques for designing robust, low power wide-OR domino logic for sub-130nm CMOS technologies," IEEE Trans 2004 Computer and Society.
6. S. O. Jung, K. W. Kim, and S. Kang, "Noise constrained power optimization for dual VT domino logic," ISCAS, pp.158--161, 2001.
7. A. Alvandpour, et. al., "A sub-130-nm conditional-keeper technique," IEEE JSSC, vol. 37, pp. 633--638, May 2002.
8. H. Mahmoodi-Meimand, Kauchic Roy, "A Leakage-Tolerant High Fan-in Dynamic circuit Design Style," IEEE Trans 2004.
9. F. Moradi, A. Peiravi, H. Mahmoodi-Meimand,"A new leakage tolerant for high fan-in domino gates," proceeding of International Conference on Microelectronics 2004.
10. A. Chandrakasan, et al, "Design of high performance microprocessor circuit," IEEE Press, Piscataway, N.J., 2000.
11. M.W. Allam, M.H. Anis, and M.I. Elmasry, "High-speed dynamic logic style for scaled-down CMOS and MTCMOS technologies," ISLPED, 2000, Page(s): 155--160.
12. G. Yang, Z. Wang, and Sung-Mo Kang, "Low power and high performance circuit technique for high fan-in dynamic gates," 2004 IEEE Proc. Computer and Society.
13. Seon-Ook Jung, et al, "Skew-tolerant High-speed (STHS) domino logic," ISCAS, Volume: 4, May 2001, Page(s):154--157.
14. V. De, et al, "Technology and design challenges for low power and high performance," ISLPED, pp. 163--168, 1999.

Index Terms

• Hardware

  • Integrated circuits

    • Logic circuits