Browse Theses

This dissertation proposes and studies the concept of an Instruction Path Coprocessor (I-COP), which is a programmable on-chip coprocessor that operates on the core processor's instructions to transform them into an internal format that can be more efficiently executed. An I-COP is highly versatile and can be used to implement many different dynamic code modifications techniques to enhance the performance of the core processor. These code modification techniques are implemented in software as I-COP programs, with the appropriate code modifications being dynamically invoked based on application behavior. Using five potential I-COP applications, two different implementations of the I-COP, one based on a traditional VLIW architecture and another based on a reconfigurable architecture, are studied and evaluated. The experimental results show that the I-COP approaches the performance of a hardwired engine while offering the advantages of a programmable one. They also demonstrate that it is possible to improve the performance of the core processor by modifying I-COP code without changing the I-COP itself. Furthermore, they demonstrate the potential of the I-COP to improve the performance of the core processor by selectively invoking the appropriate I-COP program based on application characteristics. The experimental evaluation of the reconfigurable architecture based I-COP shows that it can be implemented in as little as 3% of the area of a current high-end microprocessor. We believe that the I-COP concept is both useful and feasible, and that as dynamic code modification techniques become increasingly important in improving the performance of future high performance microprocessors, the I-COP will prove to be a valuable addition to the microarchitect's arsenal.