skip to main content
Hardware-software cosynthesis of embedded real-time multiprocessors
Publisher:
  • Princeton University
  • Computer Science Dept. Engineering Quadrangle Princeton, NJ
  • United States
ISBN:978-0-599-19599-8
Order Number:AAI9920446
Pages:
196
Bibliometrics
Skip Abstract Section
Abstract

The design of embedded systems is subject to severe cost, performance, power, and design-time constraints. With increasing use of multiple embedded cores on a single chip ( system-on-a-chip )—system designers need to implement many embedded applications using real-time system design techniques such as multiple prioritized tasks sharing multiple processing elements. Due to the increasing complexity of embedded systems, it is important to apply design automation methodology at system level to help designers find high-quality implementations that meet their design constraints, in a short period of time.

We have developed a new hardware-software co-synthesis approach to the system-level design of embedded real-time applications on heterogeneous multiprocessors . Our approach focuses on several key issues : hardware-software co-synthesis, real-time scheduling and allocation, memory hierarchy modeling and optimization, and system-level design for low energy.

We designed an efficient hierarchical scheduling algorithm for multi-rate real-time tasks on heterogeneous multiprocessors. We developed the first task-level performance model for memory hierarchies. The scheduling algorithm and the memory hierarchy model are incorporated into our hardware-software co-synthesis algorithm, which synthesizes real-time tasks onto heterogeneous multiprocessors with memory hierarchy, to meet performance constraints with a cost efficient implementation. It is the first co-synthesis algorithm that synthesizes not only the hardware and software, but also the memory hierarchy, which has significant impact on performance, cost and power of today's embedded systems. Our co-synthesis algorithm achieves improved results (in terms of lower cost of the synthesized system) compared to existing algorithms.

The co-synthesis algorithm is extended to include low energy as an optimization goal, for uniprocessor architecture (one CPU and one ASIC, plus memory hierarchy). We have built a comprehensive framework for the estimation and optimization of energy dissipation in hardware-software embedded systems. The framework, which not only analyzes energy dissipation of each individual component in the system, but more importantly, also takes into account the energy interdependencies among components, can provide significant energy savings, as shown by our experimental results.

Contributors
  • Georgia Institute of Technology
  • Princeton University

Recommendations