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An implementation technique for functional languages that has received recent attention is graph reduction, which offers opportunity for the exploitation of parallelism by multiple processors. While several proposals for parallel graph reduction machines have been made, differing terminology and approaches make these proposals difficult to compare. This paper presents a systematic approach to the study of parallel graph reduction machines, and proposes an abstract architecture for such a machine that is independent of the base language and communication network chosen for an actual implementation. The abstract architecture, in addition to serving as a foundation for the design of real machines, lends quite a bit of insight into the essence of parallel graph reduction.