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- Hwu W and Chang P (1989). Achieving high instruction cache performance with an optimizing compiler, ACM SIGARCH Computer Architecture News, 17:3, (242-251), Online publication date: 1-Jun-1989.
- Jouvelot P and Dehbonei B A unified semantic approach for the vectorization and parallelization of generalized reductions Proceedings of the 3rd international conference on Supercomputing, (186-194)
- Chang P and Hwu W Control flow optimization for supercomputer scalar processing Proceedings of the 3rd international conference on Supercomputing, (145-153)
- Hwu W and Chang P Achieving high instruction cache performance with an optimizing compiler Proceedings of the 16th annual international symposium on Computer architecture, (242-251)
- Gupta R The fuzzy barrier: a mechanism for high speed synchronization of processors Proceedings of the third international conference on Architectural support for programming languages and operating systems, (54-63)
- Dehnert J, Hsu P and Bratt J Overlapped loop support in the Cydra 5 Proceedings of the third international conference on Architectural support for programming languages and operating systems, (26-38)
- Gupta R (1989). The fuzzy barrier: a mechanism for high speed synchronization of processors, ACM SIGARCH Computer Architecture News, 17:2, (54-63), Online publication date: 1-Apr-1989.
- Dehnert J, Hsu P and Bratt J (1989). Overlapped loop support in the Cydra 5, ACM SIGARCH Computer Architecture News, 17:2, (26-38), Online publication date: 1-Apr-1989.
- Rau B, Yen D, Yen W and Towie R (2019). The Cydra 5 Departmental Supercomputer, Computer, 22:1, (12-26, 28-30, 32-35), Online publication date: 1-Jan-1989.
- Daper J Compiling on horizon Proceedings of the 1988 ACM/IEEE conference on Supercomputing, (51-52)
- Ebcioğlu K (1988). A compilation technique for software pipelining of loops with conditional jumps, ACM SIGMICRO Newsletter, 19:3, (36-41), Online publication date: 1-Sep-1988.
- Colwell R, Nix R, O'Donnell J, Papworth D and Rodman P (2019). A VLIW architecture for a trace Scheduling Compiler, IEEE Transactions on Computers, 37:8, (967-979), Online publication date: 1-Aug-1988.
- Hwu W and Chang P Exploiting parallel microprocessor microarchitectures with a compiler code generator Proceedings of the 15th Annual International Symposium on Computer architecture, (45-53)
- Lewis D A programmable hardware accelerator for compiled electrical simulation Proceedings of the 25th ACM/IEEE Design Automation Conference, (172-177)
- Hanen C Optimizing horizontal microprograms for vectorial loops with timed petri nets Proceedings of the 2nd international conference on Supercomputing, (466-477)
- Hwu W and Chang P (1988). Exploiting parallel microprocessor microarchitectures with a compiler code generator, ACM SIGARCH Computer Architecture News, 16:2, (45-53), Online publication date: 17-May-1988.
- Natour I On the control dependence in the program dependence graph Proceedings of the 1988 ACM sixteenth annual conference on Computer science, (510-519)
- Chandross J, Jagadish H and Asthana A The trap as a control flow mechanism Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, (50-52)
- Ebcioğlu K A compilation technique for software pipelining of loops with conditional jumps Proceedings of the 20th annual workshop on Microprogramming, (69-79)
- Colwell R, Nix R, O'Donnell J, Papworth D and Rodman P (1987). A VLIW architecture for a trace scheduling compiler, ACM SIGARCH Computer Architecture News, 15:5, (180-192), Online publication date: 1-Nov-1987.
- Colwell R, Nix R, O'Donnell J, Papworth D and Rodman P A VLIW architecture for a trace scheduling compiler Proceedings of the second international conference on Architectual support for programming languages and operating systems, (180-192)
- Colwell R, Nix R, O'Donnell J, Papworth D and Rodman P (1987). A VLIW architecture for a trace scheduling compiler, ACM SIGPLAN Notices, 22:10, (180-192), Online publication date: 1-Oct-1987.
- Colwell R, Nix R, O'Donnell J, Papworth D and Rodman P (1987). A VLIW architecture for a trace scheduling compiler, ACM SIGOPS Operating Systems Review, 21:4, (180-192), Online publication date: 1-Oct-1987.
Index Terms
- Bulldog: a compiler for VLSI architectures
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