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Logic Minimization Algorithms for VLSI SynthesisAugust 1984
Abstract
No abstract available.
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- de Geus A Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference Proceedings of the 23rd ACM/IEEE Design Automation Conference
- Gregory D, Bartlett K, de Geus A and Hachtel G SOCRATES Proceedings of the 23rd ACM/IEEE Design Automation Conference, (79-85)
- van Laarhoven P, Aarts E and Davio M PHIPLA—a new algorithm for logic minimization Proceedings of the 22nd ACM/IEEE Design Automation Conference, (739-743)
- Bryant R Symbolic manipulation of Boolean functions using a graphical representation Proceedings of the 22nd ACM/IEEE Design Automation Conference, (688-694)
- Agrawal P, Agrawal V and Biswas N Multiple output minimization Proceedings of the 22nd ACM/IEEE Design Automation Conference, (674-680)
- Dagenais M, Agarwal V and Rumin N The McBOOLE logic minimizer Proceedings of the 22nd ACM/IEEE Design Automation Conference, (667-673)
- Camposano R Synthesis techniques for digital systems design Proceedings of the 22nd ACM/IEEE Design Automation Conference, (475-481)
- Wei R and Sangiovanni-Vincentelli A PLATYPUS Proceedings of the 22nd ACM/IEEE Design Automation Conference, (197-203)
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