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Reviewer: Diego R. Llanos

Since its first edition in 1990, this book has rapidly become a reference text in most advanced computing architecture courses all over the world. The idea of writing a book to explain computer architecture from the performance point of view has proved its usefulness, allowing students and engineers to better understand the tradeoffs involved in the design of a computer system. The second edition, published in 1996 [1], updated the first edition’s contents, adding many new advances in hardware, from pipelined instruction level parallelism to shared bus multiprocessors to computer interconnection technologies. This third edition presents a better organization of subjects in each chapter. To fully understand the contents, a good background in computer architecture is needed. Most introductory material needed is covered by Computer organization and design: the hardware-software interface [2], an excellent introductory book in computer architecture written by the same authors, and has therefore been removed from or placed in the appendices of this book. Most of the high-quality appendices are available online, an excellent idea that keeps the book to a reasonable size. Each chapter concludes with several common sections: “Putting It All Together,” presents real-world examples of the topics covered; “Fallacies and Pitfalls,” shows common mistakes and architectural traps; and “Historical Perspective and Further Reading,” provides an absorbing description of the historic evolution of the concepts presented, together with an excellent collection of useful references and many exercises with different degrees of difficulty, some of them with their solutions. This huge work (1200 pages) is structured in eight chapters plus the appendices. Chapter 1, “Fundamentals of Computer Design,” presents the evolution of computing performance over the years and establishes an initial taxonomy of computer markets. This new classification, extensively referenced in the rest of the book, defines three categories: desktop computing, servers, and embedded computers; the latter a field that had not been covered in the previous edition. The importance of the embedded market, with its rapid growth rate in the last few years, is immense, and with its several distinguishing factors (power consumption, real-time requirements, lack of huge amounts of memory) it justifies a detailed study. Relationships between cost, price, and performance are also analyzed here. The chapter also presents a description of some basic principles of computing design, and finishes with a discussion of performance and price-performance in relation to each of the computer categories mentioned above. Chapter 2, “Instruction Set Principles and Examples,” classifies different characteristics found in an instruction set, such as the memory addressing scheme, type and size of operands, operations, and flow control. This new edition also shows those concepts in the context of digital signal processors (DSP) and media processors. As in the previous edition, the RISC concept is extensively described, together with the role of compilers in obtaining better performance. The MIPS architecture is described as a classic example of RISC machine, replacing the DLX architecture that can be found in the previous edition. The Trimedia TM32 processor, dedicated to multimedia processing, is also analyzed here, although to better understand the description, some concepts of very large instruction word (VLIW) architectures, delayed in the book until chapter 4, would be useful. Chapter 3, “Instruction-Level Parallelism and its Dynamic Exploitation,” describes some of the problems associated with the use of pipelining, branch prediction, and hardware-based speculation in the design of a new architecture. To fully understand these advanced topics, it might be necessary to have a refresher on some concepts on pipelining by reading the material provided in Appendix A. This appendix, together with chapter 3, condenses the material covered in chapters 3 and 4 of the previous edition, also reducing the overlap with the content presented in the authors’ introductory book [2]. Chapter 4, “Exploiting Instruction-Level Parallelism with Software Approaches,” shows how advanced compiler techniques can improve the performance of pipelines and multi-issue processors. The VLIW approach is also presented here, as a software solution to avoid dependency checking by the hardware. Many pages are devoted to the description of compiler techniques to exploit inherent parallelism, and how the hardware can help. It is clear that compiling for processors with significant amounts of ILP has become quite complex. The chapter concludes with an extensive description of the Intel IA-64 architecture and Itanium processor, and the Trimedia TM32 and the Transmeta Crusoe chip as examples of VLIW in the embedded space. The coverage of the memory hierarchy design in chapter 5 is simply perfect, with a complete review of cache peculiarities (such as cache miss penalty, miss rate, and hit time), together with a clear enumeration of techniques to handle each one of them. Mechanisms for reducing them by overlapping with the execution of instructions are also described. The organization of this chapter is excellent, allowing the reader to fully understand the impact of each technique in different aspects of the cache design. The chapter continues with a description of main memory organizations to help reduce latency and supply a higher bandwidth; a survey on memory technology; and an introduction to virtual memory and its relationship with caches. As in other chapters, this chapter concludes with the description of real-world examples of the topics discussed; in this case, the memory hierarchy of the Alpha 21264 and the Emotion Engine of the Sony Playstation 2 are covered, together with the Sunfire 6800 server as an example from the server market. Multiprocessors and thread-level parallelism are covered in chapter 6, and the discussion is then dedicated to storage systems and network technologies. As the authors say, multiprocessor architecture is a large and diverse field that would require an additional volume: their intention is only to focus on the mainstream of multiprocessor design. Chapter 6 contains most of the material about multiprocessors included on chapter 8 of the previous edition. A commercial workload has been added to the scientific workload that was used in the previous edition to show the behavior and performance of symmetric and distributed shared-memory architectures. A new section on multithreading architectures and their challenges is included here. Sun’s Wildfire prototype is the example chosen to show how the advantages of centralized and distributed shared memory architectures can be combined, presenting a uniform access to memory while allowing good scalability. Chapters 7 and 8 present storage systems and network technologies. In addition to the topics already presented in the second edition (buses, I/O performance measures, RAID systems), chapter 7 includes the study of failures in storage systems, with some real-world examples and statistics that are hard to find elsewhere. Benchmarking of storage performance is also included here. The design of an I/O system is more effectively explained than in the previous edition, with more elaborate examples. Chapter 8 presents the basic concepts on networking from the computer architect’s point of view. Three new sections deal with cluster technology, with a discussion on its performance challenges and some recommendations on cluster design with examples, followed by an extremely interesting description of the cluster of PCs used by the Google search engine. The chapter concludes with an additional example from the embedded world; in this case, some wireless networking concepts and the anatomy of a digital cell phone. Previous editions of this book have become a standard reference for advanced computer architecture courses and for practitioners of computer design. This new edition updates its contents to reflect the rapid evolution of the discipline and presents an improved organization of the information, especially in the chapters devoted to instruction-level parallelism and memory hierarchy. If the previous editions quickly became the reference book in the field, this new edition will surely be at least as successful as they were. Online Computing Reviews Service

Reviewer: Fernando Berzal

This excellent book, nicknamed , is the third edition of a classic that began its journey with two previous editions in the 1990s. Suffice it to say that, in computer architecture and related subjects, particularly in the study of computer design and organization, this is THE advanced textbook. If you studied computer design a few years ago, and you want to keep up to date with the latest trends and advances, you should definitely buy and read this book. If, however, you are only beginning to make some inroads into the field of computer architecture, maybe you should start with the authors () textbook [1]. is more light-hearted, and will probably spur your interest in the field and make you ask for more in the future, while is intended for those knowledgeable people who expect more than simplistic descriptions of the fundamentals. advocates for a quantitative approach, based on measurement. Any design decision should be made after extensive simulations and proper measurements on actual examples, not just on cleverly devised scenarios that tend to bias the experimental results. Often, easy-to-perform, back of the envelope calculations will suffice to evaluate competing designs. Hunches and vested (mainly commercial) interests should never replace a quantitative evaluation, or a study of cost-performance-power trade-offs. Following this approach, tackles instruction set design, studies instruction-level parallelism (both from a hardware and from a software point of view), looks at memory hierarchies in detail (a topic whose origin dates back to 1946), and analyzes the higher-level parallelism found in multiprocessors and clusters. This lengthy book even overviews storage systems and introduces networking topics. All of this is seasoned with thought-provoking comments (see, for instance, Throughput Versus Response Time, on p. 717 through p. 719), cleverly written introductions to ancillary topics (such as queuing theory, for example, on p. 720), and insightful discussions to broaden your perspective (for example in Studies on the Limitations of ILP [instruction-level parallelism], on p. 240). Parallelism is one recurring theme throughout the book. In fact, the advantages of parallel execution were already proposed in 1842 (p. 652), the era of Charles Babbages analytical engine. While there have been continuous technological advances during the last decades, computer performance has maintained a growth rate above and beyond the growth due to these technology improvements. This is because of clever ideas that make use of parallelism at the instruction and thread level. Pipelined, superscalar, very long instruction word (VLIW), explicitly parallel instruction computers (EPIC), simultaneous multithreading (SMT), and vector processors are examined, as well as multiprocessors and multicomputers, such as clusters, thus covering the entire spectrum of hardware design alternatives. The authors also discuss techniques that are used in modern optimizing compilers to improve performance. A combination of a varied set of techniques is necessary in order to keep improving performance, since parallelism at a given level is hampered both by the mismatch between hardware architecture and current software development approaches, and also by the square law of computation [2], which states that, unless simplifications are made, the amount of computation involved (hardware complexity) increases at least as fast as the square of the size of the problem (instruction complexity). Apart from its broad coverage of almost every topic that might be of interest for computer architects, stands out because of its almost unique style, which makes this book an invaluable reference. The Putting It All Together and Another View sections present real examples of actual computer systems, from the desktop, server, and embedded markets. In these sections, readers will learn about the internal organization of the Intel P6 and NetBurst microarchitectures (covering microprocessors from the Pentium Pro to the Pentium 4), the IA-64 architecture (implemented by the Itanium processor), the cluster used by the Google search engine, the innards of the Sony Playstation 2, the building blocks of a Sanyo digital camera, and even the architecture of a Nokia cell phone, as well as the MIPS instruction set, the Alpha 21264 memory hierarchy, and other interesting examples. Other outstanding sections are present in all chapters. Fallacies and Pitfalls collects some wrongly believed assumptions and widely made mistakes, as a warning sign for practitioners. Historical Perspective tries to put everything in context, describing how ideas were originated, and evolved over time due to competing forces. Comprehensive lists of exercises, to verify what you have learned and hone your skills, close the book chapters, which are complemented by a few appendices containing additional material. Some of these appendices are available online (http://www.mkp.com/CA3), and address topics such as vector processors, computer arithmetic, and coherence protocols, as well as a wide range of instruction set architectures. is definitely not for newbies, assuming they want to fully understand all the cross-cutting issues, as the title says, in those sections that discuss trade-offs and interactions among different aspects of a computer design. This apparent limitation on the target audience for the book, however, does not make it inaccessible to those new to the field. The books thorough and clear explanations fit the bill for a five-star textbook, which is worth its weight (and your wrist pain, if you get absorbed into reading this book for too long). I am looking forward to the next edition of this book. There are people who, without enough time to peruse research journals and conference proceedings, will nevertheless always be interested in understanding the innards of the latest computers from an objective and critical point of view, which is not easily found in the trade publications. Online Computing Reviews Service