*A comprehensive overview of hardware and software issues make this a "must-have" for electrical and computer engineers *Contains new material on RISC processors, performance analysis, multiprocessors and memory systems *New two-color design and illustrations illuminate the text Table of contents 1 Basic Structure of Computers 2 Machine Instructions and Programs 3 ARM, Motorola, and Intel Instruction Sets 4 Input/Output Organization 5 The Memory System 6 Arithmetic 7 Basic Processing Unit 8 Pipelining 9 Embedded Systems 10 Computer Peripherals 11 Processor Families 12 Large Computer Systems Appendix A Logic Circuits Appendix B ARM Instruction Set Appendix C Motorola 68000Instruction Set Appendix D Intel IA-32 Instruction Set Appendix E Character Codes and Number Conversion
Cited By
- Moreno C, Fischmeister S and Hasan M Non-intrusive program tracing and debugging of deployed embedded systems through side-channel analysis Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems, (77-88)
- Moreno C, Fischmeister S and Hasan M (2013). Non-intrusive program tracing and debugging of deployed embedded systems through side-channel analysis, ACM SIGPLAN Notices, 48:5, (77-88), Online publication date: 23-May-2013.
- Moreno C, Fischmeister S and Hasan M Non-intrusive program tracing and debugging of deployed embedded systems through side-channel analysis Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems, (77-88)
- Eremin E Using topic map technology in the planning of courses from the CS knowledge domain Proceedings of the Seventh Baltic Sea Conference on Computing Education Research - Volume 88, (179-182)
- Pascual L, Torrentí A, Sahuquillo J and Flich J Understanding cache hierarchy interactions with a program-driven simulator Proceedings of the 2007 workshop on Computer architecture education, (30-35)
- Eslami Y, Sheikholeslami A, Gulak P, Masui S and Mukaida K (2006). An area-efficient universal cryptography processor for smart cards, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14:1, (43-56), Online publication date: 1-Jan-2006.
- Vranesic Z and Brown S Use of HDLs in teaching of computer hardware courses Proceedings of the 2003 workshop on Computer architecture education: Held in conjunction with the 30th International Symposium on Computer Architecture, (16-es)
- Chen Y and Lee S (2000). Bounded tag fair queueing for broadband packet switching networks, Computer Communications, 23:1, (45-61), Online publication date: 1-Jan-2000.
Recommendations
Teaching computer architecture/organisation using simulators
FIE '98: Proceedings of the 28th Annual Frontiers in Education - Volume 03Experience shows that many students, especially those with little hardware background, encounter difficulties in understanding the consequences and even concepts of conventional instruction pipelining; superscalar instruction processing is even more ...
Register Organization for Enhanced On-Chip Parallelism
ASAP '04: Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International ConferenceLarge register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-flight instructions to exploit higher instruction level parallelism (ILP). ...