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The Architecture of Symbolic ComputersSeptember 1990
- Author:
- Peter M. Kogge
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Abstract
From the Publisher:
Written by a leading researcher/designer in the field,this book focuses on the design and implementation of two classes of non-Von Neumann computer architectures: for Functional (such as LISP) and Logical (such as Prolog) language computing. This represents one of the biggest steps in computer design in forty years.
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- Berezin S, Clarke E, Biere A and Zhu Y (2019). Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function, Formal Methods in System Design, 20:2, (159-186), Online publication date: 1-Mar-2002.
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- Ramanan V and Govindarajan R Resource usage models for instruction scheduling Proceedings of the 13th international conference on Supercomputing, (417-424)
- Anane R (2019). Holistic design of a programming system, ACM SIGSOFT Software Engineering Notes, 23:1, (72-76), Online publication date: 1-Jan-1998.
- Dubois M, Scheurich C and Briggs F Memory access buffering in multiprocessors 25 years of the international symposia on Computer architecture (selected papers), (320-328)
- Chang P, Mahlke S, Chen W, Warter N and Hwu W IMPACT 25 years of the international symposia on Computer architecture (selected papers), (408-417)
- Hassoun S and Ebeling C Using precomputation in architecture and logic resynthesis Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (316-323)
- Hassoun S Fine grain incremental rescheduling via architectural retiming Proceedings of the 11th international symposium on System synthesis, (158-163)
- McGraw R, Aylor J and Klenke R A top-down design environment for developing pipelined datapaths Proceedings of the 35th annual Design Automation Conference, (236-241)
- Hassoun S and Ebeling C Architectural retiming Proceedings of the 33rd annual Design Automation Conference, (708-713)
- Altman E, Govindarajan R and Gao G Scheduling and mapping Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation, (139-150)
- Altman E, Govindarajan R and Gao G (1995). Scheduling and mapping, ACM SIGPLAN Notices, 30:6, (139-150), Online publication date: 1-Jun-1995.
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- Huang I and Despain A Generating instruction sets and microarchitectures from applications Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, (391-396)
- Holmer B A tool for processor instruction set design Proceedings of the conference on European design automation, (150-155)
- Torng H and Day M (1993). Interrupt Handling for Out-of-Order Execution Processors, IEEE Transactions on Computers, 42:1, (122-127), Online publication date: 1-Jan-1993.
- Perleberg C and Smith A (2019). Branch Target Buffer Design and Optimization, IEEE Transactions on Computers, 42:4, (396-412), Online publication date: 1-Apr-1993.
- Cloutier R and Thomas D Synthesis of pipelined instruction set processors Proceedings of the 30th international Design Automation Conference, (583-588)
- Öner K and Dubois M Effects of memory latencies on non-blocking processor/cache architectures Proceedings of the 7th international conference on Supercomputing, (338-347)
- Awaga M and Takahashi H (2019). The μVP 64-Bit Vector Coprocessor, IEEE Micro, 13:5, (24-36), Online publication date: 1-Sep-1993.
- Bodin F, Charot F and Wagner C Overview of a high-performance programmable pipeline structure Proceedings of the 3rd international conference on Supercomputing, (398-409)
- Kovacs L and Gilli S Extended microcode error checking on a pipelined machine Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture, (83-87)
- Kovacs L and Gilli S (1989). Extended microcode error checking on a pipelined machine, ACM SIGMICRO Newsletter, 20:3, (83-87), Online publication date: 1-Aug-1989.
- Sanguinetti J Micro-analysis of the titans's operating pipe Proceedings of the 2nd international conference on Supercomputing, (190-196)
- Walicki J and Laughlin J (1988). Operation scheduling in reconfigurable, multifunction pipelines, ACM SIGMICRO Newsletter, 19:3, (42-45), Online publication date: 1-Sep-1988.
- Thistle M and Smith B A processor architecture for horizon Proceedings of the 1988 ACM/IEEE conference on Supercomputing, (35-41)
- Dennis J and Gao G An efficient pipelined dataflow processor architecture Proceedings of the 1988 ACM/IEEE conference on Supercomputing, (368-373)
- Hsu P and Davidson E (2019). Highly concurrent scalar processing, ACM SIGARCH Computer Architecture News, 14:2, (386-395), Online publication date: 1-May-1986.
- Dubois M, Scheurich C and Briggs F (2019). Memory access buffering in multiprocessors, ACM SIGARCH Computer Architecture News, 14:2, (434-442), Online publication date: 1-May-1986.
- Hsu P and Davidson E Highly concurrent scalar processing Proceedings of the 13th annual international symposium on Computer architecture, (386-395)
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- Kaneko H, Miki Y, Nohara S, Koya K and Araki M A 32-bit CMOS microprocessor with six-stage pipeline structure Proceedings of 1986 ACM Fall joint computer conference, (1000-1007)
- Proulx D (1984). Applications of pipelining to firmware, ACM SIGMICRO Newsletter, 15:4, (37-46), Online publication date: 1-Dec-1984.
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