From the Publisher:
Synthesis and Optimization of Digital Circuits offers a modern, up-to-date look at computer-aided design (CAD) of very large-scale integration (VLSI) circuits. In particular, this book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and/or area-optimal circuits representations from models in hardware description languages. The book provides a thorough explanation of synthesis and optimization algorithms accompanied by a sound mathematical formulation and a unified notation. The text covers the following topics: modern hardware description languages (e.g., VHDL, Verilog); architectural-level synthesis of data flow and control units, including algorithms for scheduling and resource binding; combinational logic optimization algorithms for two-level and multiple-level circuits; sequential logic optimization methods; and library binding techniques, including those applicable to FPGAs.
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- Mirhosseini M, Fazlali M, Fallah M and Lee J (2023). A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithm, The Journal of Supercomputing, 79:11, (12042-12073), Online publication date: 1-Jul-2023.
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- Muller O, Prost-Boucle A, Bourge A and Pétrot F (2019). Efficient Decompression of Binary Encoded Balanced Ternary Sequences, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27:8, (1962-1966), Online publication date: 1-Aug-2019.
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- Andriamisaina C, Coussy P, Casseau E and Chavet C (2010). High-level synthesis for designing multimode architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29:11, (1736-1749), Online publication date: 1-Nov-2010.
- Logofătu D and Dumitrescu D Parallel evolutionary approach of compaction problem using mapreduce Proceedings of the 11th international conference on Parallel problem solving from nature: Part II, (361-370)
- Yemliha T, Kandemir M, Ozturk O, Kultursay E and Muralidhara S Code scheduling for optimizing parallelism and data locality Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I, (204-216)
- Lagadec L and Picard D Smalltalk debug lives in the matrix International Workshop on Smalltalk Technologies, (11-16)
- Cong J and Minkovich K LUT-based FPGA technology mapping for reliability Proceedings of the 47th Design Automation Conference, (517-522)
- Cardoso J, Diniz P and Weinhardt M (2010). Compiling for reconfigurable computing, ACM Computing Surveys, 42:4, (1-65), Online publication date: 1-Jun-2010.
- Palaniswamy A, Goparaju M and Tragoudas S Scalable identification of threshold logic functions Proceedings of the 20th symposium on Great lakes symposium on VLSI, (269-274)
- Gilabert F, Gómez M, Medardoni S and Bertozzi D Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, (165-172)
- Del Barrio A, Molina M, Mendias J, Hermida R and Memik S Using speculative functional units in high level synthesis Proceedings of the Conference on Design, Automation and Test in Europe, (1779-1784)
- Aghera P, Krishnaswamy D, Fang D, Coskun A and Rosing T DynAHeal Proceedings of the Conference on Design, Automation and Test in Europe, (1661-1664)
- Cong J, Liu B and Xu J Coordinated resource optimization in behavioral synthesis Proceedings of the Conference on Design, Automation and Test in Europe, (1267-1272)
- Mehdipour F, Honda H, Kataoka H, Inoue K, Kataeva I, Murakami K, Akaike H and Fujimaki A Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits Proceedings of the Conference on Design, Automation and Test in Europe, (993-996)
- Zhang J, Zhang Z, Zhou S, Tan M, Liu X, Cheng X and Cong J Bit-level optimization for high-level synthesis and FPGA-based acceleration Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, (59-68)
- Cabodi G, Lavagno L, Murciano M, Kondratyev A and Watanabe Y (2010). Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques, ACM Transactions on Design Automation of Electronic Systems, 15:2, (1-34), Online publication date: 1-Feb-2010.
- Chakrapani L and Palem K A probabilistic Boolean logic for energy efficient circuit and system design Proceedings of the 2010 Asia and South Pacific Design Automation Conference, (628-635)
- Huang S, Chang C, Tu W and Pan S Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating Proceedings of the 2010 Asia and South Pacific Design Automation Conference, (480-485)
- Gajski D and Vahid F (1995). Specification and Design of Embedded Hardware-Software Systems, IEEE Design & Test, 12:1, (53-67), Online publication date: 1-Jan-2010.
- Czerwiński R and Kania D (2009). Synthesis of finite state machines for CPLDs, International Journal of Applied Mathematics and Computer Science, 19:4, (647-659), Online publication date: 1-Dec-2009.
- Verma A, Brisk P and Ienne P Iterative layering Proceedings of the 2009 International Conference on Computer-Aided Design, (797-804)
- Cong J, Liu B and Zhang Z Scheduling with soft constraints Proceedings of the 2009 International Conference on Computer-Aided Design, (47-54)
- Maftei E, Pop P and Madsen J Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, (195-204)
- Ciesielski M, Gomez-Prado D, Ren Q, Guillot J and Boutillon E (2009). Optimization of data-flow computations using canonical TED representation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28:9, (1321-1333), Online publication date: 1-Sep-2009.
- Cong J, Liu B and Zhang Z Behavior-level observability don't-cares and application to low-power behavioral synthesis Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, (139-144)
- Shin I, Paik S and Shin Y Register allocation for high-level synthesis using dual supply voltages Proceedings of the 46th Annual Design Automation Conference, (937-942)
- Choudhury M and Mohanram K Timing-driven optimization using lookahead logic circuits Proceedings of the 46th Annual Design Automation Conference, (390-395)
- Arbel E, Eisner C and Rokhlenko O Resurrecting infeasible clock-gating functions Proceedings of the 46th Annual Design Automation Conference, (160-165)
- Dal D and Mansouri N (2009). Power optimization with power islands synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28:7, (1025-1037), Online publication date: 1-Jul-2009.
- Cong J, Fan Y and Xu J (2009). Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture, ACM Transactions on Design Automation of Electronic Systems, 14:3, (1-31), Online publication date: 1-May-2009.
- Dimitroulakos G, Kostaras N, Galanis M and Goutis C (2009). Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays, The Journal of Supercomputing, 48:2, (115-151), Online publication date: 1-May-2009.
- Chatterjee D, DeOrio A and Bertacco V GCS Proceedings of the Conference on Design, Automation and Test in Europe, (1332-1337)
- Golshan S and Bozorgzadeh E SEU-aware resource binding for modular redundancy based designs on FPGAs Proceedings of the Conference on Design, Automation and Test in Europe, (1124-1129)
- Paik S, Shin I and Shin Y HLS-l Proceedings of the Conference on Design, Automation and Test in Europe, (1112-1117)
- Fazlali M, Fallah M, Zolghadr M and Zakerolhosseini A A New Datapath Merging Method for Reconfigurable System Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications, (157-168)
- Nielsen S, Sparsø J and Madsen J (2009). Behavioral synthesis of asynchronous circuits using syntax directed translation as backend, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:2, (248-261), Online publication date: 1-Feb-2009.
- Soviani C, Hadžic I and Edwards S (2009). Synthesis and optimization of pipelined packet processors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28:2, (231-244), Online publication date: 1-Feb-2009.
- Ko H and Nicolici N (2009). Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28:2, (285-297), Online publication date: 1-Feb-2009.
- Li C and Carloni L (2009). Leveraging local intracore information to increase global performance in block-based design of systems-on-chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28:2, (165-178), Online publication date: 1-Feb-2009.
- Huang S and Cheng C Timing driven power gating in high-level synthesis Proceedings of the 2009 Asia and South Pacific Design Automation Conference, (173-178)
- Lucas G, Cromar S and Chen D FastYield Proceedings of the 2009 Asia and South Pacific Design Automation Conference, (61-66)
- Hong Y, Huang Y and Huang J Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture Proceedings of the 2009 Asia and South Pacific Design Automation Conference, (19-24)
- Mehta G, Stander J, Baz M, Hunsaker B and Jones A (2009). Interconnect customization for a hardware fabric, ACM Transactions on Design Automation of Electronic Systems, 14:1, (1-32), Online publication date: 1-Jan-2009.
- Stanczyk U On optimisation of the rough set-based decision rule extraction Proceedings of the 8th conference on Applied computer scince, (296-301)
- Gaujal B and Mairesse J (2008). Minimization of circuit registers: Retiming revisited, Discrete Applied Mathematics, 156:18, (3498-3505), Online publication date: 1-Nov-2008.
- Noori H, Mehdipour F, Murakami K, Inoue K and Saheb Zamani M (2008). An architecture framework for an adaptive extensible processor, The Journal of Supercomputing, 45:3, (313-340), Online publication date: 1-Sep-2008.
- Basççiftçi F and Kahramanli S A novel approach for fast covering the Boolean sets Proceedings of the 8th conference on Systems theory and scientific computation, (260-263)
- Choi E, Shin C, Kim T and Shin Y Power-gating-aware high-level synthesis Proceedings of the 2008 international symposium on Low Power Electronics & Design, (39-44)
- Aboalsamh H A Boolean algebraic framework for association and pattern mining Proceedings of the 12th WSEAS international conference on Computers, (940-949)
- Jung H, Yang H and Ha S (2008). Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis, Journal of Signal Processing Systems, 52:1, (13-34), Online publication date: 1-Jul-2008.
- Kirischian V, Geurkov V and Kirischian L A multi-mode video-stream processor with cyclically reconfigurable architecture Proceedings of the 5th conference on Computing frontiers, (105-106)
- Qiu M and Wu J Energy saving for memory with loop scheduling and prefetching Proceedings of the 18th ACM Great Lakes symposium on VLSI, (155-158)
- Koes D and Goldstein S Near-optimal instruction selection on dags Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization, (45-54)
- Qiu M, Sha E, Liu M, Lin M, Hua S and Yang L (2008). Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP, Journal of Parallel and Distributed Computing, 68:4, (443-455), Online publication date: 1-Apr-2008.
- Chantem T, Dick R and Hu X Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs Proceedings of the conference on Design, automation and test in Europe, (288-293)
- Ditmar J, McKeever S and Wilson A (2008). Area optimisation for field-programmable gate arrays in SystemC hardware compilation, International Journal of Reconfigurable Computing, 2008, (1-14), Online publication date: 1-Feb-2008.
- Abdel-Kader R (2008). Particle swarm optimization for constrained instruction scheduling, VLSI Design, 2008:4, (1-7), Online publication date: 1-Jan-2008.
- Su F and Chakrabarty K (2008). High-level synthesis of digital microfluidic biochips, ACM Journal on Emerging Technologies in Computing Systems, 3:4, (1-32), Online publication date: 1-Jan-2008.
- Barkalov A, Titarenko L and Chmielewski S (2007). Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM, International Journal of Applied Mathematics and Computer Science, 17:4, (565-575), Online publication date: 1-Dec-2007.
- Chavet C, Andriamisaina C, Coussy P, Casseau E, Juin E, Urard P and Martin E A design flow dedicated to multi-mode architectures for DSP applications Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, (604-611)
- Kuo Y, Chang Y, Chang S and Marek-Sadowska M Engineering change using spare cells with constant insertion Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, (544-547)
- Kim T and Liu X Compatibility path based binding algorithm for interconnect reduction in high level synthesis Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, (435-441)
- Jung J and Kim T Timing variation-aware high-level synthesis Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, (424-428)
- Li C and Carloni L Using functional independence conditions to optimize the performance of latency-insensitive systems Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, (32-39)
- Mittal G, Zaretsky D, Tang X and Banerjee P (2007). An overview of a compiler for mapping software binaries to hardware, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15:11, (1177-1190), Online publication date: 1-Nov-2007.
- Stitt G and Vahid F Thread warping Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, (93-98)
- Chabini N A Heuristic for reducing dynamic power dissipation in clocked sequential designs Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (64-74)
- Gopalakrishnan S and Kalla P (2007). Optimization of polynomial datapaths using finite ring algebra, ACM Transactions on Design Automation of Electronic Systems, 12:4, (49-es), Online publication date: 1-Sep-2007.
- Galanis M, Dimitroulakos G, Tragoudas S and Goutis C (2008). Speedups in embedded systems with a high-performance coprocessor datapath, ACM Transactions on Design Automation of Electronic Systems, 12:3, (1-22), Online publication date: 17-Aug-2007.
- Stitt G and Vahid F (2008). Binary synthesis, ACM Transactions on Design Automation of Electronic Systems, 12:3, (1-30), Online publication date: 17-Aug-2007.
- F. J, Santos L and Santos L An automatically-retargetable time-constraint-driven instruction scheduler for post-compiling optimization of embedded code Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation, (86-95)
- Stallmann M and Brglez F High-contrast algorithm behavior Proceedings of the 2007 workshop on Experimental computer science, (12-es)
- Verma A, Brisk P and Ienne P Progressive decomposition Proceedings of the 44th annual Design Automation Conference, (404-409)
- Dimitroulakos G, Galanis M, Kostaras N and Goutis C A unified evaluation framework for coarse grained reconfigurable array architectures Proceedings of the 4th international conference on Computing frontiers, (161-172)
- Garg A, Xenarios I, Mendoza L and DeMicheli G An efficient method for dynamic analysis of gene regulatory networks and in silico gene perturbation experiments Proceedings of the 11th annual international conference on Research in computational molecular biology, (62-76)
- Angiolini F, Jamaa M, Atienza D, Benini L and De Micheli G Interactive presentation: Improving the fault tolerance of nanometric PLA designs Proceedings of the conference on Design, automation and test in Europe, (570-575)
- Zilic Z, Radecka K and Kazamiphur A Reversible circuit technology mapping from non-reversible specifications Proceedings of the conference on Design, automation and test in Europe, (558-563)
- Ciesielski M, Askar S, Gomez-Prado D, Guillot J and Boutillon E Data-flow transformations using Taylor expansion diagrams Proceedings of the conference on Design, automation and test in Europe, (455-460)
- Balluchi A, Mazzi E and Vincentelli A Complexity reduction for the design of interacting controllers Proceedings of the 10th international conference on Hybrid systems: computation and control, (46-60)
- Dal D and Mansouri N A high-level register optimization technique for minimizing leakage and dynamic power Proceedings of the 17th ACM Great Lakes symposium on VLSI, (517-520)
- Stewart K and Tragoudas S (2007). Managing the power resources of sensor networks with performance considerations, Computer Communications, 30:5, (1122-1135), Online publication date: 1-Mar-2007.
- Su F and Zeng J (2007). Computer-Aided Design and Test for Digital Microfluidics, IEEE Design & Test, 24:1, (60-70), Online publication date: 1-Jan-2007.
- Cong J, Fan Y and Jiang W Platform-based resource binding using a distributed register-file microarchitecture Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, (709-715)
- Hung W, Wu X and Xie Y Guaranteeing performance yield in high-level synthesis Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, (303-309)
- Zhou Y, Sokolov D and Yakovlev A Cost-aware synthesis of asynchronous circuits based on partial acknowledgement Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, (158-163)
- Park J and Mooney V (2006). Sleepy stack leakage reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14:11, (1250-1263), Online publication date: 1-Nov-2006.
- Reimer A, Schulz A and Nebel W Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs Proceedings of the 2006 international symposium on Low power electronics and design, (151-154)
- Galanis M, Dimitroulakos G and Goutis C (2006). Partitioning Methodology for Heterogeneous Reconfigurable Functional Units, The Journal of Supercomputing, 38:1, (17-34), Online publication date: 1-Oct-2006.
- Mehdipour F, Noori H, Zamani M, Murakami K, Sedighi M and Inoue K An integrated temporal partitioning and mapping framework for handling custom instructions on a reconfigurable functional unit Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture, (219-230)
- Mehdipour F, Noori H, Zamani M, Murakami K, Inoue K and Sedighi M Custom instruction generation using temporal partitioning techniques for a reconfigurable functional unit Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing, (722-731)
- Soviani C, Hadžić I and Edwards S Synthesis of high-performance packet processing pipelines Proceedings of the 43rd annual Design Automation Conference, (679-682)
- Verma A and Ienne P Towards the automatic exploration of arithmetic-circuit architectures Proceedings of the 43rd annual Design Automation Conference, (445-450)
- Harmanani H and Abas H A method for the minimum coloring problem using genetic algorithms Proceedings of the 17th IASTED international conference on Modelling and simulation, (487-492)
- Galanis M, Dimitroulakos G and Goutis C Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware Proceedings of the 20th international conference on Parallel and distributed processing, (198-198)
- Dimitroulakos G, Galanis M and Goutis C Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures Proceedings of the 20th international conference on Parallel and distributed processing, (113-113)
- Mehdipour F, Zamani M, Ahmadifar H, Sedighi M and Murakami K Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework Proceedings of the 20th international conference on Parallel and distributed processing, (308-308)
- Logofatu D and Drechsler R Efficient evolutionary approaches for the data ordering problem with inversion Proceedings of the 2006 international conference on Applications of Evolutionary Computing, (320-331)
- Chen D, Cong J and Xu J (2006). Optimal simultaneous module and multivoltage assignment for low power, ACM Transactions on Design Automation of Electronic Systems, 11:2, (362-386), Online publication date: 1-Apr-2006.
- Raghuraman K, Wang H and Tragoudas S Minimizing FPGA Reconfiguration Data at Logic Level Proceedings of the 7th International Symposium on Quality Electronic Design, (219-224)
- Cherroun H, Darte A and Feautrier P Scheduling under resource constraints using dis-equations Proceedings of the conference on Design, automation and test in Europe: Proceedings, (1067-1072)
- Ruggiero M, Guerri A, Bertozzi D, Poletti F and Milano M Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip Proceedings of the conference on Design, automation and test in Europe: Proceedings, (3-8)
- Ekpanyapong M, Waterwai T and Lim S Statistical Bellman-Ford algorithm with an application to retiming Proceedings of the 2006 Asia and South Pacific Design Automation Conference, (959-964)
- Yoo J, Feng X, Choi K, Chung E and Choi K Worst case execution time analysis for synthesized hardware Proceedings of the 2006 Asia and South Pacific Design Automation Conference, (905-910)
- Ho Q, Massicotte D and Dahmane A (2006). FPGA implementation of an MUD based on cascade filters for a WCDMA system, EURASIP Journal on Advances in Signal Processing, 2006, (69-69), Online publication date: 1-Jan-2006.
- Han Y, Kim S and Kim C Jaguar Proceedings of the Second international conference on Embedded Software and Systems, (386-397)
- Lee D, Abdul Gaffar A, Mencer O and Luk W (2005). Optimizing Hardware Function Evaluation, IEEE Transactions on Computers, 54:12, (1520-1531), Online publication date: 1-Dec-2005.
- Ramarao P and Tyagi A An integrated partitioning and scheduling based branch decoupling Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture, (252-268)
- Witte E, Chattopadhyay A, Schliebusch O and Kammler D Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation Proceedings of the 2005 International Conference on Computer Design, (193-199)
- Yoon S, Nardini C, Benini L and De Micheli G (2005). Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams, IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2:4, (339-354), Online publication date: 1-Oct-2005.
- Ghodrat M, Givargis T and Nicolau A Equivalence checking of arithmetic expressions using fast evaluation Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, (147-156)
- Pozzi L and Ienne P Exploiting pipelining to relax register-file port constraints of instruction-set extensions Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, (2-10)
- Vuletić M, Dubach C, Pozzi L and Ienne P Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (243-248)
- McGee P, Nowick S and Coffman E Efficient performance analysis of asynchronous systems based on periodicity Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (225-230)
- Quan G, Davis J, Devarkal S and Buell D High-level synthesis for large bit-width multipliers on FPGAs Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (213-218)
- Stewart K and Tragoudas S An ILP based management protocol for wireless networks Proceedings of the 9th WSEAS International Conference on Communications, (1-6)
- Lee J and Mooney V (2005). An o(min(m, n)) parallel deadlock detection algorithm, ACM Transactions on Design Automation of Electronic Systems, 10:3, (573-586), Online publication date: 1-Jul-2005.
- Koushanfar F, Hong I and Potkonjak M (2005). Behavioral synthesis techniques for intellectual property protection, ACM Transactions on Design Automation of Electronic Systems, 10:3, (523-545), Online publication date: 1-Jul-2005.
- Su F and Chakrabarty K Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips Proceedings of the 42nd annual Design Automation Conference, (825-830)
- Li X, Stallmann M and Brglez F Effective bounding techniques for solving unate and binate covering problems Proceedings of the 42nd annual Design Automation Conference, (385-390)
- Abdollahi A and Pedram M A new canonical form for fast boolean matching in logic synthesis and verification Proceedings of the 42nd annual Design Automation Conference, (379-384)
- Meng Y, Brown A, Iltis R, Sherwood T, Lee H and Kastner R MP core Proceedings of the 42nd annual Design Automation Conference, (297-302)
- Alsharqawi A and Ejnioui A Synthesis of Self-Resetting Stage Logic Pipelines Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design, (260-262)
- Zhou K and McDonald J Multi-GHz SiGe design methodologies for reconfigurable computing Proceedings of the 15th ACM Great Lakes symposium on VLSI, (207-212)
- Wang G, Gong W and Kastner R Instruction scheduling using MAX-MIN ant system optimization Proceedings of the 15th ACM Great Lakes symposium on VLSI, (44-49)
- Dimitroulakos G, Galanis M and Goutis C A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
- Galanis M, Milidonis A, Theodoridis G, Soudris D and Goutis C A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
- Tosun S, Ozturk O, Mansouri N, Arvas E, Kandemir M, Xie Y and Hung W An ILP Formulation for Reliability-Oriented High-Level Synthesis Proceedings of the 6th International Symposium on Quality of Electronic Design, (364-369)
- Tosun S, Mansouri N, Arvas E, Kandemir M, Xie Y and Hung W Reliability-Centric Hardware/Software Co-Design Proceedings of the 6th International Symposium on Quality of Electronic Design, (375-380)
- Galanis M, Milidonis A, Theodoridis G, Soudris D and Goutis C A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms Proceedings of the conference on Design, Automation and Test in Europe - Volume 3, (247-252)
- Galanis M, Milidonis A, Theodoridis G, Soudris D and Goutis C (2005). A method for partitioning applications in hybrid reconfigurable architectures, Design Automation for Embedded Systems, 10:1, (27-47), Online publication date: 1-Mar-2005.
- Cong J, Fan Y, Han G, Jagannathan A, Reinman G and Zhang Z Instruction set extension with shadow registers for configurable processors Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, (99-106)
- Mittal G, Zaretsky D, Memik G and Banerjee P Automatic extraction of function bodies from software binaries Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (928-931)
- Cong J, Fan Y, Han G, Lin Y, Xu J, Zhang Z and Cheng X Bitwidth-aware scheduling and binding in high-level synthesis Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (856-861)
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- Beidas R and Zhu J Scalable interprocedural register allocation for high level synthesis Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (511-516)
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- Meribout M and Motomura M (2004). A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems, IEEE Transactions on Computers, 53:12, (1508-1522), Online publication date: 1-Dec-2004.
- Verma A and Ienne P Improved use of the carry-save representation for the synthesis of complex arithmetic circuits Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, (791-798)
- Su F and Chakrabarty K Architectural-level synthesis of digital microfluidics-based biochips Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, (223-228)
- Bjesse P and Boralv A DAG-aware circuit compression for formal verification Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, (42-49)
- Harkin J, McGinnity T and Maguire L (2004). Modeling and optimizing run-time reconfiguration using evolutionary computation, ACM Transactions on Embedded Computing Systems, 3:4, (661-685), Online publication date: 1-Nov-2004.
- Styles H and Luk W (2004). Exploiting Program Branch Probabilities in Hardware Compilation, IEEE Transactions on Computers, 53:11, (1408-1419), Online publication date: 1-Nov-2004.
- Kandemir M, Kadayif I and Chen G Compiler-directed code restructuring for reducing data TLB energy Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, (98-103)
- Chen G, Kang B, Kandemir M, Vijaykrishnan N, Irwin M and Chandramouli R (2004). Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices, IEEE Transactions on Parallel and Distributed Systems, 15:9, (795-809), Online publication date: 1-Sep-2004.
- Bhattacharyya S and Murthy P (2004). The CBP Parameter, Journal of VLSI Signal Processing Systems, 38:2, (131-146), Online publication date: 1-Sep-2004.
- Jeong C and Nowick S Fast hazard detection in combinational circuits Proceedings of the 41st annual Design Automation Conference, (592-595)
- Bañeres D, Cortadella J and Kishinevsky M A recursive paradigm to solve Boolean relations Proceedings of the 41st annual Design Automation Conference, (416-421)
- Mittal G, Zaretsky D, Tang X and Banerjee P Automatic translation of software binaries onto FPGAs Proceedings of the 41st annual Design Automation Conference, (389-394)
- Wang W, Raghunathan A, Lakshminarayana G and Jha N (2004). Input space adaptive design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12:6, (590-602), Online publication date: 1-Jun-2004.
- Zaretsky D, Mittal G, Tang X and Banerjee P Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs Proceedings of the 14th ACM Great Lakes symposium on VLSI, (397-400)
- Udrescu M, Prodan L and Vlǎdutiu M Using HDLs for describing quantum circuits Proceedings of the 1st conference on Computing frontiers, (96-110)
- De La Luz V, Kadayif I, Kandemir M and Sezer U (2004). Access Pattern Restructuring for Memory Energy, IEEE Transactions on Parallel and Distributed Systems, 15:4, (289-303), Online publication date: 1-Apr-2004.
- Manquinho V and Marques-Silva J (2004). Satisfiability-Based Algorithms for Boolean Optimization, Annals of Mathematics and Artificial Intelligence, 40:3-4, (353-372), Online publication date: 1-Mar-2004.
- Cong J, Fan Y, Han G and Zhang Z Application-specific instruction generation for configurable processor architectures Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, (183-189)
- Liu Y, Wang K and Hwang T Crosstalk Minimization in Logic Synthesis for PLA Proceedings of the conference on Design, automation and test in Europe - Volume 2
- Bansal N, Gupta S, Dutt N, Nicolau A and Gupta R Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures Proceedings of the conference on Design, automation and test in Europe - Volume 1
- Debnath D and Sasao T Efficient computation of canonical form for Boolean matching in large libraries Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (591-596)
- Najaf-Abadi H A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (86-91)
- Chen D and Cong J Register binding and port assignment for multiplexer optimization Proceedings of the 2004 Asia and South Pacific Design Automation Conference, (68-73)
- Sharad S and Shukla S Optimizing system models for simulation efficiency Formal methods and models for system design, (317-330)
- Chatterjee M and Pradhan D (2003). A BIST Pattern Generator Design for Near-Perfect Fault Coverage, IEEE Transactions on Computers, 52:12, (1543-1558), Online publication date: 1-Dec-2003.
- Di Blas A, Jagota A and Hughey R (2003). A Range-Compaction Heuristic for Graph Coloring, Journal of Heuristics, 9:6, (489-506), Online publication date: 1-Dec-2003.
- Cong J, Fan Y, Han G, Yang X and Zhang Z Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
- Zhang Z, Fan Y, Potkonjak M and Cong J Gradual Relaxation Techniques with Applications to Behavioral Synthesis Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
- Wang Q and Roy S RTL Power Optimization with Gate-Level Accuracy Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
- Plessl C and Platzner M (2003). Instance-Specific Accelerators for Minimum Covering, The Journal of Supercomputing, 26:2, (109-129), Online publication date: 1-Sep-2003.
- Fomina E, Keevallik A, Kruus M and Sudnitson A A decomposition procedure for register-transfer level power management Proceedings of the 4th international conference conference on Computer systems and technologies: e-Learning, (26-31)
- Chantrapornchai C Rapid prototyping methodology and environments for fuzzy applications Proceedings of the 2003 international conference on Computational science, (940-949)
- Liang X and Jean J (2003). Mapping of generalized template matching onto reconfigurable computers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11:3, (485-498), Online publication date: 1-Jun-2003.
- Lange S and Kebschull U Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Kim E, Saito H, Lee J, Lee D, Nakamura H and Nanya T Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Chiou L, Bhunia S and Roy K Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
- Leijten-Nowak K and van Meerbergen J An FPGA architecture with enhanced datapath functionality Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, (195-204)
- Kim E, Lee D, Saito H, Nakamura H, Lee J and Nanya T Performance optimization of synchronous control units for datapaths with variable delay arithmetic units Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (816-819)
- Banerjee P An overview of a compiler for mapping MATLAB programs onto FPGAs Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (477-482)
- Cho G and Chen T On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS Proceedings of the 16th International Conference on VLSI Design
- Gupta S, Dutt N, Gupta R and Nicolau A SPARK Proceedings of the 16th International Conference on VLSI Design
- Wang W, Jha N, Raghunathan A and Dey S High-level Synthesis of Multi-process Behavioral Descriptions Proceedings of the 16th International Conference on VLSI Design
- McCluskey E Switching theory Encyclopedia of Computer Science, (1727-1731)
- Byun S, Lee S, Tewfik A and Ahn B A SVD-based fragile watermarking scheme for image authentication Proceedings of the 1st international conference on Digital watermarking, (170-178)
- Sun F, Ravi S, Raghunathan A and Jha N Synthesis of custom processors based on extensible platforms Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (641-648)
- Huang C, Ravi S, Raghunathan A and Jha N High-level synthesis of distributed logic-memory architectures Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (564-571)
- Chowdhary A and Gupta R (2002). A Methodology for Synthesis of Data Path Circuitse, IEEE Design & Test, 19:6, (90-100), Online publication date: 1-Nov-2002.
- Wong J, Megerian S and Potkonjak M Forward-looking objective functions Proceedings of the 39th annual Design Automation Conference, (904-909)
- Kölbi A, Kukula J, Antreich K and Damiano R Handling special constructs in symbolic simulation Proceedings of the 39th annual Design Automation Conference, (105-110)
- Drini M and Kirovski D Behavioral synthesis via engineering change Proceedings of the 39th annual Design Automation Conference, (18-21)
- Bjuréus P, Millberg M and Jantsch A FPGA resource and timing estimation from Matlab execution traces Proceedings of the tenth international symposium on Hardware/software codesign, (31-36)
- O'Neil T and Sha E Minimizing resources in a repeating schedule for a split-node data-flow graph Proceedings of the 12th ACM Great Lakes symposium on VLSI, (136-141)
- Zhao M and Sapatnekar S (2002). Technology mapping algorithms for domino logic, ACM Transactions on Design Automation of Electronic Systems, 7:2, (306-335), Online publication date: 1-Apr-2002.
- Kirshnaswamy V, Hasteer G and Banerjee P (2002). Automatic Parallelization of Compiled Event Driven VHDL Simulation, IEEE Transactions on Computers, 51:4, (380-394), Online publication date: 1-Apr-2002.
- Ferrandi F, Fummi F and Sciuto D (2002). Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications, IEEE Transactions on Computers, 51:2, (200-215), Online publication date: 1-Feb-2002.
- Ramanujam J, Deshpande S, Hong J and Kandemir M A Heuristic for Clock Selection in High-Level Synthesis Proceedings of the 2002 Asia and South Pacific Design Automation Conference
- Haubelt C, Teich J, Richter K and Ernst R Flexibility/cost-tradeoffs of platform-based systems Embedded processor design challenges, (38-56)
- Graeb H, Zizala S, Eckmueller J and Antreich K The sizing rules method for analog integrated circuit design Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (343-349)
- Kim D, Jung J, Lee S, Jeon J and Choi K Behavior-to-placed RTL synthesis with performance-driven placement Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (320-325)
- Haldar M, Nayak A, Choudhary A and Banerjee P A system for synthesizing optimized FPGA hardware from MATLAB Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (314-319)
- Peymandoust A and De Micheli G Symbolic algebra and timing driven data-flow synthesis Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (300-305)
- Kandemir M, Sezer U and Delaluz V Improving memory energy using access pattern classification Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (201-206)
- Benini L and De Micheli G Logic synthesis for low power Logic Synthesis and Verification, (197-223)
- Narasimhan N, Teica E, Radhakrishnan R, Govindarajan S and Vemuri R (2001). Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis, Formal Methods in System Design, 19:3, (237-273), Online publication date: 1-Oct-2001.
- Kim D, Shin D and Choi K Low power pipelining of linear systems Proceedings of the 2001 international symposium on Low power electronics and design, (225-230)
- Wang W, Raghunathan A, Lakshminarayana G and Jha N Input space adaptive design Proceedings of the 38th annual Design Automation Conference, (738-743)
- Bruni D, Bogliolo A and Benini L Statistical design space exploration for application-specific unit synthesis Proceedings of the 38th annual Design Automation Conference, (641-646)
- Doboli A and Vemuri R Integrated high-level synthesis and power-net routing for digital design under switching noise constraints Proceedings of the 38th annual Design Automation Conference, (629-634)
- Zhao M and Sapatnekar S A new structural pattern matching algorithm for technology mapping Proceedings of the 38th annual Design Automation Conference, (371-376)
- Peymandoust A and De Micheli G Using symbolic algebra in algorithmic level DSP synthesis Proceedings of the 38th annual Design Automation Conference, (277-282)
- Theobald M and Nowick S Transformations for the synthesis and optimization of asynchronous distributed control Proceedings of the 38th annual Design Automation Conference, (263-268)
- Jacome M and de Veciana G Lower bound on latency for VLIW ASIP datapaths Readings in hardware/software co-design, (477-484)
- Kalavade A and Lee E The extended partitioning problem Readings in hardware/software co-design, (293-312)
- Mathur A, Dasdan A and Gupta R Rate analysis for embedded systems Readings in hardware/software co-design, (207-221)
- Edwards S, Lavagno L, Lee E and Sangiovanni-Vincentelli A Design of embedded systems Readings in hardware/software co-design, (86-107)
- De Micheli G and Gupta R Hardware/software co-design Readings in hardware/software co-design, (30-44)
- Antola A, Ferrandi F, Piuri V and Sami M (2001). Semiconcurrent Error Detection in Data Paths, IEEE Transactions on Computers, 50:5, (449-465), Online publication date: 1-May-2001.
- Shiu P, Tan Y and Mooney V A novel parallel deadlock detection algorithm and architecture Proceedings of the ninth international symposium on Hardware/software codesign, (73-78)
- Arnold M and Corporaal H Designing domain-specific processors Proceedings of the ninth international symposium on Hardware/software codesign, (61-66)
- Constantinides G, Cheung P and Luk W Heuristic datapath allocation for multiple wordlength systems Proceedings of the conference on Design, automation and test in Europe, (791-797)
- Zhu J Static memory allocation by pointer analysis and coloring Proceedings of the conference on Design, automation and test in Europe, (785-790)
- Ouaiss I and Vemuri R Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers Proceedings of the conference on Design, automation and test in Europe, (650-657)
- Doboli A Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints Proceedings of the conference on Design, automation and test in Europe, (612-619)
- Macchiarulo L, Benini L and Macii E On-the-fly layout generation for PTL macrocells Proceedings of the conference on Design, automation and test in Europe, (546-551)
- Chiusano S, di Carlo S, Prinetto P and Wunderlich H On applying the set covering model to reseeding Proceedings of the conference on Design, automation and test in Europe, (156-161)
- Economakos G, Oikonomakos P, Panagopoulos I, Poulakis I and Papakonstantinou G Behavioral synthesis with systemC Proceedings of the conference on Design, automation and test in Europe, (21-25)
- Balasa F, Geurts W, Catthoor F and De Man H Solving large scale assignment problems in high-level synthesis by approximative quadratic programming Proceedings of the 11th Great Lakes symposium on VLSI, (19-24)
- Chen D, Cong J, Ercegovac M and Huang Z Performance-driven mapping for CPLD architectures Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, (39-47)
- Haldar M, Nayak A, Choudhary A and Banerjee P Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (645-648)
- Vemuri R, Govindarajan S, Ouaiss I, Kaul M, Srinivasan V, Radhakrishnan S, Sundaraman S, Ganesan S, Pandey A and Lakshmikanthan P Automated design synthesis and partitioning for adaptive reconfigurable hardware Hardware implementation of intelligent systems, (3-52)
- Jacome M, de Veciana G and Lapinskii V Exploring performance tradeoffs for clustered VLIW ASIPs Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, (504-510)
- Karri R, Kim K and Potkonjak M (2000). Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors, IEEE Transactions on Computers, 49:11, (1272-1284), Online publication date: 1-Nov-2000.
- Mitra S and McCluskey E COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS Proceedings of the 2000 IEEE International Test Conference
- Psarakis M, Gizopoulos D, Paschalis A and Zorian Y (2000). Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays, IEEE Transactions on Computers, 49:10, (1083-1099), Online publication date: 1-Oct-2000.
- Quer S, Cabodi G, Camurati P, Lavagno L, Sentovich E and Brayton R (2000). Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks, Formal Methods in System Design, 17:2, (107-134), Online publication date: 1-Oct-2000.
- Kruse L, Schmidt E, Jochens G, Stammermann A and Nebel W Lower bound estimation for low power high-level synthesis Proceedings of the 13th international symposium on System synthesis, (180-185)
- Symbolic Binding for Clustered VLIW ASIPs Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
- Efficient Place and Route for Pipeline Reconfigurable Architectures Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
- Nemani M and Tiwari V Macro-driven circuit design methodology for high-performance datapaths Proceedings of the 37th Annual Design Automation Conference, (661-666)
- Anand R, Jacome M and de Veciana G Heuristic tradeoffs between latency and energy consumption in register assignment Proceedings of the eighth international workshop on Hardware/software codesign, (115-119)
- Cong J and Sarrafzadeh M Incremental physical design Proceedings of the 2000 international symposium on Physical design, (84-92)
- Cong J and Hwang Y (2000). Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs, ACM Transactions on Design Automation of Electronic Systems, 5:2, (193-225), Online publication date: 1-Apr-2000.
- Benini L and Micheli G (2000). System-level power optimization, ACM Transactions on Design Automation of Electronic Systems, 5:2, (115-192), Online publication date: 1-Apr-2000.
- Heinrich-Litan L and Molitor P (2000). Least Upper Bounds for the Size of OBDDs Using Symmetry Properties, IEEE Transactions on Computers, 49:4, (360-368), Online publication date: 1-Apr-2000.
- Fummi F and Sciuto D (2000). A Hierarchical Test Generation Approach for Large Controllers, IEEE Transactions on Computers, 49:4, (289-302), Online publication date: 1-Apr-2000.
- Farrahi A, Hathaway D, Wang M and Sarrafzadeh M Quality of EDA CAD Tools Proceedings of the 1st International Symposium on Quality of Electronic Design
- Chung K, Kim T and Liu C Behavioral-level partitioning for low power design in control-dominated application Proceedings of the 10th Great Lakes symposium on VLSI, (156-161)
- Chantrapornchai C, Sha E and Hu X Efficient algorithms for acceptable design exploration Proceedings of the 10th Great Lakes symposium on VLSI, (139-142)
- Manquinho V and Marques-Silva J On using satisfiability-based pruning techniques in covering algorithms Proceedings of the conference on Design, automation and test in Europe, (356-363)
- Ganesan S and Vemuri R Technology mapping and retargeting for field-programmable analog arrays Proceedings of the conference on Design, automation and test in Europe, (58-65)
- Mansouri N and Vemuri R (2000). Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs, Formal Methods in System Design, 16:1, (59-91), Online publication date: 1-Jan-2000.
- Wilsey P Web-based analysis and distributed IP Proceedings of the 31st conference on Winter simulation: Simulation---a bridge to the future - Volume 2, (1445-1453)
- Fummi F, Sciuto D and Serra M (1999). Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal, IEEE Transactions on Computers, 48:12, (1305-1323), Online publication date: 1-Dec-1999.
- Kirovski D and Potkonjak M Localized watermarking Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (596-599)
- Jacome M and de Veciana G Lower bound on latency for VLIW ASIP datapaths Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (261-269)
- Ruan S, Shang R, Lai F, Chen S and Huang X A bipartition-codec architecture to reduce power in pipelined circuits Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (84-90)
- Hong I, Potkonjak M and Papaefthymiou M (1999). Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors, Design Automation for Embedded Systems, 4:4, (311-327), Online publication date: 1-Oct-1999.
- Ewing R (1999). Technology Road Map to Methodologies for Mixed-Signal System Designand Simulation, Journal of VLSI Signal Processing Systems, 22:2, (123-134), Online publication date: 1-Sep-1999.
- Ewing R (1999). Technology Road Map to Methodologies for Mixed-Signal System Design and Simulation, Journal of VLSI Signal Processing Systems, 22:2, (123-134), Online publication date: 1-Sep-1999.
- Ewing R (1999). Technology Road Map to Methodologies for Mixed-Signal System Design& Simulation, Analog Integrated Circuits and Signal Processing, 20:3, (213-225), Online publication date: 1-Sep-1999.
- Bogliolo A, Benini L, Riccó B and De Micheli G Efficient switching activity computation during high-level synthesis of control-dominated designs Proceedings of the 1999 international symposium on Low power electronics and design, (127-132)
- Kruse L, Schmidt E, Jochens G and Nebel W Lower and upper bounds on the switching activity in scheduled data flow graphs Proceedings of the 1999 international symposium on Low power electronics and design, (115-120)
- Falkowski B (1999). A Note on the Polynomial Form of Boolean Functions and Related Topics, IEEE Transactions on Computers, 48:8, (860-864), Online publication date: 1-Aug-1999.
- Nourani M and Papachristou C (1999). Structural Fault Testing of Embedded Cores Using Pipelining, Journal of Electronic Testing: Theory and Applications, 15:1-2, (129-144), Online publication date: 1-Aug-1999.
- Hong I and Potkonjak M Behavioral synthesis techniques for intellectual property protection Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (849-854)
- Kim H, Ha D and Takahashi T On ILP formulations for built-in self-testable data path synthesis Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (742-747)
- Kirovski D and Potkonjak M Engineering change Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (604-609)
- Lakshminarayana G, Raghunathan A, Khouri K, Jha N and Dey S Common-case computation Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (56-61)
- Chang D and Marek-Sadowska M (1999). Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs, IEEE Transactions on Computers, 48:6, (565-578), Online publication date: 1-Jun-1999.
- Cardoso J and Neto H Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
- Taubin A, Kondratyev A, Cortadella J and Lavagno L Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
- Beister J, Eckstein G and Wollowski R From STG to Extended-Burst-Mode Machines Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
- Rhodes D and Wolf W Overhead effects in real-time preemptive schedules Proceedings of the seventh international workshop on Hardware/software codesign, (193-197)
- Jacome M, de Veciana G and Akturan C Resource constrained dataflow retiming heuristics for VLIW ASIPs Proceedings of the seventh international workshop on Hardware/software codesign, (12-16)
- Kalla P and Ciesielski M Performance driven resynthesis by exploiting retiming-induced state register equivalence Proceedings of the conference on Design, automation and test in Europe, (125-es)
- dos Santos L and Jess J Exploiting state equivalence on the fly while applying code motion and speculation Proceedings of the conference on Design, automation and test in Europe, (120-es)
- Kaul M and Vemuri R Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs Proceedings of the conference on Design, automation and test in Europe, (43-es)
- Hassoun S Fine grain incremental rescheduling via architectural retiming Proceedings of the 11th international symposium on System synthesis, (158-163)
- Bolchini C, Fornaciari W, Salice F and Sciuto D Concurrent error detection at architectural level Proceedings of the 11th international symposium on System synthesis, (72-75)
- Pena J and Oliveira A A new algorithm for the reduction of incompletely specified finite state machines Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (482-489)
- Séméria L and De Micheli G SpC: synthesis of pointers in C Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (340-346)
- Chowdhary A, Kale S, Saripella P, Sehgal N and Gupta R A general approach for regularity extraction in datapath circuits Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (332-339)
- Iyer B and Ciesielski M Reencoding for cycle-time minimization under fixed encoding length Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (312-315)
- Kirovski D, Hwang Y, Potkonjak M and Cong J Intellectual property protection by watermarking combinational logic synthesis solutions Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (194-198)
- Bolchini C, Salice F and Sciuto D (1998). Fault Analysis for Networks with Concurrent Error Detection, IEEE Design & Test, 15:4, (66-74), Online publication date: 1-Oct-1998.
- Parulkar I, Gupta S and Breuer M (1998). Allocation Techniques for Reducing BIST Area Overhead ofData Paths, Journal of Electronic Testing: Theory and Applications, 13:2, (149-166), Online publication date: 1-Oct-1998.
- Krishnaswamy V and Banerjee P Parallel compiled event driven VHDL simulation Proceedings of the 12th international conference on Supercomputing, (297-304)
- Benini L, De Micheli G, Lioy A, Macii E, Odasso G and Poncino M Computational kernels and their application to sequential power optimization Proceedings of the 35th annual Design Automation Conference, (764-769)
- Anderson J and Brown S Technology mapping for large complex PLDs Proceedings of the 35th annual Design Automation Conference, (698-703)
- Bauer J, Bershteyn M, Kaplan I and Vyedin P A reconfigurable logic machine for fast event-driven simulation Proceedings of the 35th annual Design Automation Conference, (668-671)
- Nemani M and Najm F Delay estimation VLSI circuits from a high-level view Proceedings of the 35th annual Design Automation Conference, (591-594)
- Chang S and Cheng D Efficient Boolean division and substitution Proceedings of the 35th annual Design Automation Conference, (342-347)
- Kravets V and Sakallah K M32 Proceedings of the 35th annual Design Automation Conference, (336-341)
- Chang D and Marek-Sadowska M Partitioning sequential circuits on dynamically reconfiguable FPGAs Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, (161-167)
- Coudert O A new paradigm for dichotomy-based constrained encoding Proceedings of the conference on Design, automation and test in Europe, (830-834)
- Li J and Gupta R An algorithm to determine mutually exclusive operations in behavioral descriptions Proceedings of the conference on Design, automation and test in Europe, (457-465)
- Hansen C, Kunzmann A and Rosenstiel W Verification by simulation comparison using interface synthesi Proceedings of the conference on Design, automation and test in Europe, (436-445)
- Parulkar I, Gupta S and Breuer M Scheduling and module assignment for reducing BIST resources Proceedings of the conference on Design, automation and test in Europe, (66-73)
- Srinivasan V, Radhakrishnan S and Vemuri R Hardware/software partitioning with integrated hardware design space exploration Proceedings of the conference on Design, automation and test in Europe, (28-35)
- Kagaris D and Tragoudas S Maximum independent sets on transitive graphs and their applications in testing and CAD Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (736-740)
- Fuhrer R and Nowick S OPTIMIST Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (308-315)
- Chen C and Küçükçakar K High-level scheduling model and control synthesis for a broad range of design applications Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (236-243)
- Cortadella J, Kishinevsky M, Kondratyev A, Lavagno L, Pastor E and Yakovlev A Decomposition and technology mapping of speed-independent circuits using Boolean relations Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (220-227)
- Nemani M and Najm F High-level area and power estimation for VLSI circuits Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (114-119)
- Li J and Gupta R Decomposition of timed decision tables and its use in presynthesis optimizations Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (22-27)
- Vuillod P, Benini L and De Micheli G Generalized matching from theory to application Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (13-20)
- Mitra S, Avra L and McCluskey E SCAN SYNTHESIS FOR ONE-HOT SIGNALS Proceedings of the 1997 IEEE International Test Conference
- Vuillod P, Benini L and De Micheli G Re-mapping for low power under tight timing constraints Proceedings of the 1997 international symposium on Low power electronics and design, (287-292)
- Shin D and Choi K Low power high level synthesis by increasing data correlation Proceedings of the 1997 international symposium on Low power electronics and design, (62-67)
- Dawid H, Koch K and Stahl J ADPCM codec Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
- Peixoto H and Jacome M Algorithm and architecture-level design space exploration using hierarchical data flows Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
- Hsieh C, Pedram M, Mehta G and Rastgar F Profile-driven program synthesis for evaluation of system power dissipation Proceedings of the 34th annual Design Automation Conference, (576-581)
- Kim K, Karri R and Potkonjak M Synthesis of application specific programmable processors Proceedings of the 34th annual Design Automation Conference, (353-358)
- Willems M, Bürsgens V, Keding H, Grötker T and Meyr H System level fixed-point design based on an interpolative approach Proceedings of the 34th annual Design Automation Conference, (293-298)
- Coudert O Exact coloring of real-life graphs is easy Proceedings of the 34th annual Design Automation Conference, (121-126)
- Liu T, Sajid K, Aziz A and Singhal V Optimizing designs containing black boxes Proceedings of the 34th annual Design Automation Conference, (113-116)
- Maheshwari N and Sapatnekar S An improved algorithm for minimum-area retiming Proceedings of the 34th annual Design Automation Conference, (2-7)
- Buonanno G, Pugassi M and Sami M A high-level synthesis approach to design of fault-tolerant systems Proceedings of the 15th IEEE VLSI Test Symposium
- Keutzer K, Newton A and Shenoy N The future of logic synthesis and physical design in deep-submicron process geometries Proceedings of the 1997 international symposium on Physical design, (218-224)
- Hu T Physical design Proceedings of the 1997 international symposium on Physical design, (207-210)
- Bjorn-Jorgensen P and Madsen J Critical path driven cosynthesis for heterogeneous target architectures Proceedings of the 5th International Workshop on Hardware/Software Co-Design
- Teich J, Blickle T and Thiele L An evolutionary approach to system-level synthesis Proceedings of the 5th International Workshop on Hardware/Software Co-Design
- Bogliolo A, Benini L and De Micheli G Adaptive least mean square behavioral power modeling Proceedings of the 1997 European conference on Design and Test
- Coudert O Solving Graph Optimization Problems with ZBDDs Proceedings of the 1997 European conference on Design and Test
- Sriram S and Lee E (1997). Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors, Journal of VLSI Signal Processing Systems, 15:3, (207-220), Online publication date: 1-Mar-1997.
- Sriram S and Lee E (1997). Determining the Order of Processor Transactions in StaticallyScheduled Multiprocessors, Journal of VLSI Signal Processing Systems, 15:3, (207-220), Online publication date: 1-Mar-1997.
- Kalavade A and Lee E (1997). The Extended Partitioning Problem, Design Automation for Embedded Systems, 2:2, (125-163), Online publication date: 1-Mar-1997.
- Singh M and Nowick S Synthesis for Logical Initializability of Synchronous Finite State Machines Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
- Iyer B and Ciesielski M Metamorphosis Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, (614-617)
- Pradhan D, Paul D and Chatterjee M VERILAT Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, (88-95)
- Xiaoqing W and Saluja K A new method towards achieving global optimality in technology mapping Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, (9-12)
- Blythe S and Walker R Toward a Practical Methodology for Completely Characterizing the Optimal Design Space Proceedings of the 9th international symposium on System synthesis
- Benini L, Vuillod P, de Micheli G and Coelho C Synthesis of low-power selectively-clocked systems from high-level specification Proceedings of the 9th international symposium on System synthesis
- Muench A, Glesner M and Wehn N An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions Proceedings of the 9th international symposium on System synthesis
- Bennour I and Albouhamid E (1996). Lower bounds on the iteration time and the initiation interval of functional pipelining and loop folding, Design Automation for Embedded Systems, 1:4, (333-355), Online publication date: 1-Oct-1996.
- Sami M, Antola A and Piuri V A high-level synthesis approach to optimum design of self-checking circuits Proceedings of the conference on European design automation, (382-387)
- Chang J and Pedram M Module assignment for low power Proceedings of the conference on European design automation, (376-381)
- Gerez S and Woutersen E Assignment of storage values to sequential read-write memories Proceedings of the conference on European design automation, (302-307)
- Lin Y and Wu T Storage optimization by replacing some flip-flops with latches Proceedings of the conference on European design automation, (296-301)
- Senn M, Schneider P and Wurth B Power analysis for sequential circuits at logic level Proceedings of the conference on European design automation, (22-27)
- Pradhan D, Chatterjee M, Swarna M and Kunz W Gate-level synthesis for low-power using new transformations Proceedings of the 1996 international symposium on Low power electronics and design, (297-300)
- Coudert O On solving covering problems Proceedings of the 33rd annual Design Automation Conference, (197-202)
- Wagner K and Dey S High-level synthesis for testability Proceedings of the 33rd annual Design Automation Conference, (131-136)
- Li J and Gupta R HDL optimization using timed decision tables Proceedings of the 33rd annual Design Automation Conference, (51-54)
- Favalli M, Benini L and de Micheli G Design for Testability of Gated-Clock FSMs Proceedings of the 1996 European conference on Design and Test
- Narasimhan N, Vemuri R and Roy J Synchronous Controller Models for Synthesis from Communicating VHDL Processes Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
- Balakrishnan A and Chakradhar S Retiming with logic duplication transformation Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
- Katkoori S, Roy J and Vemuri R A Hierarchical Register Optimization Algorithm for Behavioral Synthesis Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
- Kužnar R and Brglez F PROP Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, (644-649)
- Chatterjee M, Pradhan D and Kunz W LOT Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, (318-325)
- Chaudhuri S, Blythe S and Walker R An exact methodology for scheduling in a 3D design space Proceedings of the 8th international symposium on System synthesis, (78-83)
- Benini L and De Micheli G Transformation and synthesis of FSMs for low-power gated-clock implementation Proceedings of the 1995 international symposium on Low power design, (21-26)
- Chang J and Pedram M Register allocation and binding for low power Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, (29-35)
- Gajski D and Ramachandran L (1994). Introduction to High-Level Synthesis, IEEE Design & Test, 11:4, (44-54), Online publication date: 1-Oct-1994.
- Benini L, Siegel P and De Micheli G (1994). Saving Power by Synthesizing Gated Clocks for Sequential Circuits, IEEE Design & Test, 11:4, (32-41), Online publication date: 1-Oct-1994.
- Saito H, Imai M and Yoneda T A task allocation method for the DTTR scheme based on task scheduling of fault patterns 2016 IEEE International Symposium on Circuits and Systems (ISCAS), (237-240)
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