- Author:
- Rainer Leupers
From the Publisher:
The building blocks of today's embedded systems-on-a-chip are complex IP components and programmable processor cores. This means that more and more system functionality is implemented in software rather than in custom hardware. In turn, this indicates a growing need for high-level language compilers, capable of generating efficient code for embedded processors. However, traditional compiler technology hardly keeps pace with new developments in embedded processor architectures. Many existing compilers for DSPs and multimedia processors therefore produce code of insufficient quality with respect to performance and/or code size, and a large part of software for embedded systems is still being developed in assembly languages. As both embedded software as well as processor architectures are getting more and more complex, assembly programming clearly violates the demands for a short time-to-market and high dependability in embedded system design. The goal of this book is to provide new methods and techniques to software and compiler developers, that help to make the necessary step from assembly programming to the use of compilers also in embedded system design.
Code Optimization Techniques for Embedded Processors discusses the state-of-the-art in the area of compilers for embedded processors. It presents a collection of new code optimization techniques, dedicated to DSP and multimedia processors. These include: compiler support for DSP address generation units, efficient mapping of data flow graphs to irregular architectures, exploitation of SIMD and conditional instructions, as well as function inlining under code size constraints. Comprehensive experimental evaluations are given for real-life processors, that indicate the code quality improvements which can be achieved as compared to earlier techniques. In addition, C compiler frontend issues are discussed from a practical viewpoint.
Code Optimization Techniques for Embedded Processors is intended for researchers and engineers active in software development for embedded systems, and for compiler developers in academia and industry.
Cited By
Carvalho J, Sousa B, Araújo M and Bigonha M The Register Allocation and Instruction Scheduling Challenge Proceedings of the 21st Brazilian Symposium on Programming Languages, (1-9)- Ari M (2016). A multipurpose test and measurement module with touchscreen and computer interface for engineering and technical education, Computer Applications in Engineering Education, 24:6, (905-913), Online publication date: 1-Nov-2016.
- Shokry H and El-Boghdadi H (2012). On Heuristic Solutions to the Simple Offset Assignment Problem in Address-Code Optimization, ACM Transactions on Embedded Computing Systems (TECS), 11:3, (1-17), Online publication date: 1-Sep-2012.
- Salamy H and Ramanujam J (2012). Storage Optimization through Offset Assignment with Variable Coalescing, ACM Transactions on Embedded Computing Systems, 11S:1, (1-23), Online publication date: 1-Jun-2012.
- Colby M, Nasroullahi E and Tumer K Optimizing ballast design of wave energy converters using evolutionary algorithms Proceedings of the 13th annual conference on Genetic and evolutionary computation, (1739-1746)
- Hohenauer M, Engel F, Leupers R, Ascheid G and Meyr H (2009). A SIMD optimization framework for retargetable compilers, ACM Transactions on Architecture and Code Optimization, 6:1, (1-27), Online publication date: 30-Mar-2009.
- Keinert J, Streubūhr M, Schlichter T, Falk J, Gladigau J, Haubelt C, Teich J and Meredith M (2009). SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), 14:1, (1-23), Online publication date: 1-Jan-2009.
- Bungo J (2008). The use of compiler optimizations for embedded systems software, XRDS: Crossroads, The ACM Magazine for Students, 15:1, (8-15), Online publication date: 1-Sep-2008.
- Haubelt C, Schlichter T, Keinert J and Meredith M SystemCoDesigner Proceedings of the 45th annual Design Automation Conference, (580-585)
- Fan K, Park H, Kudlur M and Mahlke S Modulo scheduling for highly customized datapaths to increase hardware reusability Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization, (124-133)
- Ali H, El-Boghdadi H and Shaheen S A new heuristic for SOA problem based on effective tie break function Proceedings of the 11th international workshop on Software & compilers for embedded systems, (53-59)
- Tanaka H, Takeuchi Y, Sakanushi K, Imai M, Tagawa H, Ota Y and Matsumoto N (2007). Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A:12, (2800-2809), Online publication date: 1-Dec-2007.
- Salamy H and Ramanujam J An effective heuristic for simple offset assignment with variable coalescing Proceedings of the 19th international conference on Languages and compilers for parallel computing, (158-172)
- Hiroaki T, Takeuchi Y, Sakanushi K, Imai M, Ota Y, Matsumoto N and Nakagawa M Pack instruction generation for media pUsing multi-valued decision diagram Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, (154-159)
- Ren G, Wu P and Padua D Optimizing data permutations for SIMD devices Proceedings of the 27th ACM SIGPLAN Conference on Programming Language Design and Implementation, (118-131)
- Ren G, Wu P and Padua D (2006). Optimizing data permutations for SIMD devices, ACM SIGPLAN Notices, 41:6, (118-131), Online publication date: 11-Jun-2006.
- Leventhal S, Yuan L, Bambha N, Bhattacharyya S and Qu G DSP address optimization using evolutionary algorithms Proceedings of the 2005 workshop on Software and compilers for embedded systems, (91-98)
- Kudriavtsev A and Kogge P (2019). Generation of permutations for SIMD processors, ACM SIGPLAN Notices, 40:7, (147-156), Online publication date: 12-Jul-2005.
- Kudriavtsev A and Kogge P Generation of permutations for SIMD processors Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, (147-156)
- Bouyssounouse B and Sifakis J Tools for programming, code generation, and design Embedded Systems Design, (63-71)
- Kudlur M, Fan K, Chu M, Ravindran R, Clark N and Mahlke S FLASH Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
- Hohenauer M, Scharwaechter H, Karuri K, Wahlen O, Kogel T, Leupers R, Ascheid G, Meyr H, Braun G and van Someren H A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models Proceedings of the conference on Design, automation and test in Europe - Volume 2
- Jan S, de Dios P and Edwards S Porting a Network Cryptographic Service to the RMC2000 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
- Kim J, Jung S, Paek Y and Uh G Experience with a retargetable compiler for a commercial network processor Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, (178-187)
- Kessler C and Bednarski A (2019). Optimal integrated code generation for clustered VLIW architectures, ACM SIGPLAN Notices, 37:7, (102-111), Online publication date: 17-Jul-2002.
- Lorenz M, Wehmeyer L and Dräger T (2019). Energy aware compilation for DSPs with SIMD instructions, ACM SIGPLAN Notices, 37:7, (94-101), Online publication date: 17-Jul-2002.
- Leupers R (2002). Compiler Design Issues for Embedded Processors, IEEE Design & Test, 19:4, (51-58), Online publication date: 1-Jul-2002.
- Kessler C and Bednarski A Optimal integrated code generation for clustered VLIW architectures Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems, (102-111)
- Lorenz M, Wehmeyer L and Dräger T Energy aware compilation for DSPs with SIMD instructions Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems, (94-101)
- Wagner J and Leupers R C Compiler Design for an Industrial Network Processor Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems, (155-164)
- Wagner J and Leupers R C Compiler Design for an Industrial Network Processor Proceedings of the ACM SIGPLAN workshop on Languages, compilers and tools for embedded systems, (155-164)
- Wagner J and Leupers R (2019). C Compiler Design for an Industrial Network Processor, ACM SIGPLAN Notices, 36:8, (155-164), Online publication date: 1-Aug-2001.
- Lim S, Kim J and Choi K Scheduling-based code size reduction in processors with indirect addressing mode Proceedings of the ninth international symposium on Hardware/software codesign, (165-169)
- Dutt N, Nicolau A, Tomiyama H and Halambi A New directions in compiler technology for embedded systems (embedded tutorial) Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (409-414)
Recommendations
Graph-based code selection techniques for embedded processors
Code selection is an important task in code generation for programmable processors, where the goal is to find an efficient mapping of machine-independent intermediate code to processor-specific machine instructions. Traditional approaches to code ...
Code Optimization Techniques in Embedded DSP Microprocessors
We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code generation methods typically result in inefficient code. In this ...