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Reviewer: Lanfranco Lopriore

The author is a member of the Reduced Instruction Set Computer (RISC) project team at the University of California at Berkeley. This project was aimed at the design and subsequent implementation of a RISC architecture. As a result, two single-chip processors have been developed, RISC I and RISC II. The author has been mainly involved in the design, layout, debugging, and testing phases of the development of the RISC II chip. This book is the author's PhD thesis. The thesis received the 1984 ACM award for the best doctoral dissertation and, as such, has been published by the MIT Press. Chapter 1 provides a short introduction to the RISC concept and the evolution of the RISC project. Then, an in-depth analysis of machine instruction usage is carried out in Chapter 2, with reference to high-level languages such as FORTRAN and C. The application environment includes numeric computation, text processing, and CAD. A considerable amount of data from the literature is collected and carefully reviewed. Chapter 3 shows how the results of the analysis have been included in the design of the RISC I and II instruction set (the reader can find an exact definition of the instruction set in an appendix). Certain important aspects of the RISC architecture are also presented, and these include the multiwindow register file and the pipeline organization. The performance of the RISC instruction set is discussed in terms of both memory requirements and execution times. In this evaluation, a comparison is made with several processors, such as the Digital VAX-11/780 and PDP-11/70, the Zilog Z8002, and the Motorola M68000. The importance of keeping the microarchitecture in mind when designing the instruction set is stressed. In the author's opinion, “an understanding of the implementation is essential in making architectural decisions that lead to a high-performance processor.” Chapter 4 deals with the design and layout of the RISC II chip. The data path is considered, and tradeoffs are presented. Possible alternative solutions are illustrated. The discussion focuses on timings, with particular respect to the pipeline. The organization of the RISC control is also considered. The simple instruction format and a careful opcode assignment result in an easy instruction decoding. A comparison is made with the complexity of the control sections of other microprocessors. The advantages of the reduced instruction set approach are emphasized. Chapter 5 reports on the debugging and testing phases of the development of the RISC II chip. The author stresses that “the sophisticated simulation tools available in today's CAD environments make it feasible to debug a VLSI design almost completely before fabrication.” The RISC experience seems to demonstrate that this approach is both viable and advantageous. Finally, Chapter 6 discusses a number of architectural issues raised by the need to improve utilization of the silicon area in VLSI processor chips. In the author's opinion, it is far better to provide a single-chip processor with time-saving features, such as cache memories and pipelining, than to extend the instruction set to include scarcely used complex instructions. The importance of separate data and instruction caches and of multiport memory systems is argued. A comparison is made between a conventional data cache and a multiwindow register file organization, with the conclusions favoring the latter. A multiwindow register file with variable-size windows is presented as an alternative to the fixed-size windows of the RISC architecture. The problem of fast control transfers is considered in depth, and possible improvements to the solution implemented in the RISC chips are presented. The book features a Bibliography consisting of 58 references. Included are several published papers and technical reports authored by the members of the RISC project team. This book is a careful report of all the phases of the design and development of a VLSI processor. It is recommended literature for researchers and practitioners involved in similar projects. However, VLSI design is only one aspect of the book, which also contains an excellent presentation of advanced concepts in computer architecture. As such, it is absorbing reading for every computer architect. The points of view and the conclusions of the author are often quite debatable, but the presentation never lacks in-depth considerations of the salient aspects of the problems being considered. This is the case, for instance, in the analysis of the motivations in favor of the reduced instruction set, as well as for the discussions concerning on-chip caches and multiple register sets. In fact, the reduced instruction set is only one of the challenges issued to processor architects by the RISC project. As far as classroom utilization is concerned, this reviewer highly recommends this book for case study analysis in graduate-level courses on computer architecture and VLSI design.