Skip header Section
Skip Bibliometrics Section
The RISC-V Reader: An Open Architecture AtlasSeptember 2017
- Authors:
- David Patterson,
- Andrew Waterman
Skip Abstract Section
Abstract
This Beta Edition of The RISC-V Reader was retired 11/9/17, as the First Edition is now available
Cited By
Murshed M, Murphy C, Hou D, Khan N, Ananthanarayanan G and Hussain F (2021). Machine Learning at the Network Edge: A Survey, ACM Computing Surveys, 54:8, (1-37), Online publication date: 30-Nov-2022.- Hennessy J and Patterson D (2019). A new golden age for computer architecture, Communications of the ACM, 62:2, (48-60), Online publication date: 28-Jan-2019.
Recommendations
A microcoded RISC
A new, microcoded, RISC-type system is proposed and presented. The microcode is stored in a 256 x 64 PROM Nanomemory in the CPU. The 8-bit opcode of each instruction is a direct address to the Nanomemory. Each Nanomemory 64-bit word (horizontal ...
The HP PA-8000 RISC CPU
The PA-8000 RISC CPU is the first implementation of a new generation of microprocessors from Hewlett-Packard Company. The processor was designed for high-end systems and to support the new 64-bit PA-RISC 2.0 architecture. The aggressive four-way ...