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Cong J and Wang J PolySA: Polyhedral-Based Systolic Array Auto-Compilation 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (1-8)

Causapruno G, Urgese G, Vacca M, Graziano M and Zamboni M (2015). Protein Alignment Systolic Array Throughput Optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23:1, (68-77), Online publication date: 1-Jan-2015.

Causapruno G, Vacca M, Graziano M and Zamboni M (2015). Interleaving in Systolic-Arrays: A Throughput Breakthrough, IEEE Transactions on Computers, 64:7, (1940-1953), Online publication date: 1-Jul-2015.

Ahmed N, Mateev N and Pingali K Synthesizing transformations for locality enhancement of imperfectly-nested loop nests ACM International Conference on Supercomputing 25th Anniversary Volume, (299-310)

Pingali K Author retrospective for synthesizing transformations for locality enhancement of imperfectly-nested loop nests ACM International Conference on Supercomputing 25th Anniversary Volume, (56-58)

Stamoulias I and Manolakos E (2013). Parallel architectures for the kNN classifier -- design of soft IP cores and FPGA implementations, ACM Transactions on Embedded Computing Systems, 13:2, (1-21), Online publication date: 1-Sep-2013.

Randjelovic D Reducing the number of processors elements in systolic arrays for matrix multiplication Proceedings of the 11th WSEAS international conference on Software Engineering, Parallel and Distributed Systems, and proceedings of the 9th WSEAS international conference on Engineering Education, (42-47)

Ali H (2012). CP-based SBHT-RLS algorithms for tracking channel estimates in multicarrier modulation systems, Journal of Electrical and Computer Engineering, 2012, (1-12), Online publication date: 1-Jan-2012.

Romero-Aguirre E, Parra-Michel R, Carrasco-Alvarez R and Orozco-Lugo A (2012). Configurable transmitter and systolic channel estimator architectures for data-dependent superimposed training communications systems, International Journal of Reconfigurable Computing, 2012, (4-4), Online publication date: 1-Jan-2012.

Ratuszniak P Processor array design with the use of genetic algorithm Proceedings of the 8th international conference on Large-Scale Scientific Computing, (238-246)

Atoche A, Roman D and Shkvarko Y (2010). Experiment design regularization-based hardware/software codesign for real-time enhanced imaging in uncertain remote sensing environment, EURASIP Journal on Advances in Signal Processing, 2010, (1-21), Online publication date: 1-Feb-2010.

Atoche A, Roman D and Shkvarko Y Reconfigurable architecture of systolic array processors for remote sensing applications Proceedings of the 9th WSEAS international conference on signal, speech and image processing, and 9th WSEAS international conference on Multimedia, internet & video technologies, (162-167)

Meher P (2009). Systolic and non-systolic scalable modular designs of finite field multipliers for reed-solomon codec, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:6, (747-757), Online publication date: 1-Jun-2009.

Benkrid K, Liu Y and Benkrid A (2009). A highly parameterized and efficient FPGA-based skeleton for pairwise biological sequence alignment, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17:4, (561-570), Online publication date: 1-Apr-2009.

Hourani R, Jenkal R, Davis W and Alexander W (2009). Automated Design Space Exploration for DSP Applications, Journal of Signal Processing Systems, 56:2-3, (199-216), Online publication date: 1-Sep-2009.

Meher P, Ha Y and Lee C An optimized design for serial-parallel finite field multiplication over GF(2) based on all-one polynomials Proceedings of the 2009 Asia and South Pacific Design Automation Conference, (210-215)

Stuijk S and Basten T (2008). Analyzing concurrency in streaming applications, Journal of Systems Architecture: the EUROMICRO Journal, 54:1-2, (124-144), Online publication date: 1-Jan-2008.

Michailidis P and Margaritis K (2008). Processor array architectures for flexible approximate string matching, Journal of Systems Architecture: the EUROMICRO Journal, 54:1-2, (35-54), Online publication date: 1-Jan-2008.

Thinh T and Kittitornkun S Systolic array for string matching in NIDS Proceedings of the Fourth IASTED Asian Conference on Communication Systems and Networks, (84-88)

Zekri A and Sedukhin S Performance evaluation of basic linear algebra subroutines on a matrix co-processor Proceedings of the 7th international conference on Parallel processing and applied mathematics, (1190-1199)

Maslennikow O, Lepekha V, Sergiyenko A, Tomas A and Wyrzykowski R Parallel implementation of Cholesky LLT-algorithm in FPGA-based processor Proceedings of the 7th international conference on Parallel processing and applied mathematics, (137-147)

Huang J and Li H A parallel architecture for motion estimation and DCT computation in MPEG-2 encoder Proceedings of the 7th international conference on Algorithms and architectures for parallel processing, (210-221)

Galilee B, Mamalet F, Renaudin M and Coulon P (2007). Parallel Asynchronous Watershed Algorithm-Architecture, IEEE Transactions on Parallel and Distributed Systems, 18:1, (44-56), Online publication date: 1-Jan-2007.

Zekri A and Sedukhin S The general matrix multiply-add operation on 2D torus Proceedings of the 20th international conference on Parallel and distributed processing, (309-309)

Michailidis P and Margaritis K Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs Proceedings of the 20th international conference on Parallel and distributed processing, (211-211)

Sinnen O, Sousa L and Eika Sandnes F (2006). Toward a Realistic Task Scheduling Model, IEEE Transactions on Parallel and Distributed Systems, 17:3, (263-275), Online publication date: 1-Mar-2006.

Gebali F and Rafiq A (2006). Processor Array Architectures for Deep Packet Classification, IEEE Transactions on Parallel and Distributed Systems, 17:3, (241-252), Online publication date: 1-Mar-2006.

Huang Y, Chen C, Tsai C, Shen C and Chen L (2006). Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results, Journal of VLSI Signal Processing Systems, 42:3, (297-320), Online publication date: 1-Mar-2006.

Kim H and Lee S Low complexity systolic architecture for modular multiplication over GF(2m) Proceedings of the 6th international conference on Computational Science - Volume Part I, (634-640)

Ayala-Rincón M, Llanos C, Jacobi R and Hartenstein R (2006). Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic, ACM Transactions on Design Automation of Electronic Systems, 11:2, (251-281), Online publication date: 1-Apr-2006.

Lian C, Huang Y, Fang H, Chang Y and Chen L JPEG, MPEG-4, and H.264 Codec IP Development Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, (1118-1119)

Zekri A and Sedukhin S Computationally efficient parallel matrix-matrix multiplication on the torus Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems, (219-226)

Kim C, Lee S and Kim S 2-D discrete cosine transform (DCT) on meshes with hierarchical control modes Proceedings of the Second Iberian conference on Pattern Recognition and Image Analysis - Volume Part I, (675-682)

Kim H and Jeon I Semi-systolic architecture for modular multiplication over GF(2m) Proceedings of the 5th international conference on Computational Science - Volume Part III, (912-915)

Meher P Area-Time efficient systolic architecture for the DCT Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture, (787-794)

Kim C, Kwon S and Hong C A fast digit-serial systolic multiplier for finite field GF(2) Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (1268-1271)

Lee J and Song G Design of an application-specific PLD architecture Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (1244-1247)

Yan Z and Sarwate D Area-efficient two-dimensional architectures for finite field inversion and division Proceedings of the 15th ACM Great Lakes symposium on VLSI, (116-121)

Yi Y, Woods R, Ting L and Cowan C (2005). High Speed FPGA-Based Implementations of Delayed-LMS Filters, Journal of VLSI Signal Processing Systems, 39:1-2, (113-131), Online publication date: 1-Jan-2005.

Michailidis P and Margaritis K (2005). New Processor Array Architectures for the Longest Common Subsequence Problem, The Journal of Supercomputing, 32:1, (51-69), Online publication date: 1-Apr-2005.

Teifel J and Manohar R Highly pipelined asynchronous FPGAs Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, (133-142)

Ayala-Rincón M, Jacobi R, Carvalho L, Llanos C and Hartenstein R Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic Proceedings of the 17th symposium on Integrated circuits and system design, (248-253)

Teifel J and Manohar R (2004). An Asynchronous Dataflow FPGA Architecture, IEEE Transactions on Computers, 53:11, (1376-1392), Online publication date: 1-Nov-2004.

Wu C, Wu C, Shieh M and Hwang Y (2004). High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m), IEEE Transactions on Computers, 53:3, (375-380), Online publication date: 1-Mar-2004.

Hong J and Wu C (2003). Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11:3, (474-484), Online publication date: 1-Jun-2003.

Singh A, Mukherjee A, Macchiarulo L and Marek-Sadowska M (2003). PITIA, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11:3, (354-363), Online publication date: 1-Jun-2003.

Lee H and Fortes J (2003). Generation of Injective and Reversible Modular Mappings, IEEE Transactions on Parallel and Distributed Systems, 14:1, (1-12), Online publication date: 1-Jan-2003.

Lee J and Song G Implementation of the super-systolic array for convolution Proceedings of the 2003 Asia and South Pacific Design Automation Conference, (491-494)

Kittitornkun S and Hu Y (2003). Processor Array Synthesis from Shift-Variant Deep Nested Do Loops, The Journal of Supercomputing, 24:3, (229-249), Online publication date: 1-Mar-2003.

Bednara M, Hannig F and Teich J Generation of distributed loop control Embedded processor design challenges, (154-170)

Chai S and Wills D (2002). Systolic Opportunities for Multidimensional Data Streams, IEEE Transactions on Parallel and Distributed Systems, 13:4, (388-398), Online publication date: 1-Apr-2002.

Purcell T Parallel ray tracing on a chip Practical parallel rendering, (329-336)

Zhong L and Jha N Interconnect-aware high-level synthesis for low power Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, (110-117)

Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1 Proceedings of the 2nd International Symposium on Quality Electronic Design

Bakhanovich S and Likhoded N (2001). Scheduling Functions for Spatiotemporal Mapping of d-Dimensional Algorithms with Homogeneous Dependences on (d-2)-Dimensional Parallel Architectures, Cybernetics and Systems Analysis, 37:3, (434-442), Online publication date: 1-May-2001.

Buck J, Ha S, Lee E and Messerschmitt D Ptolemy Readings in hardware/software co-design, (527-543)

Heron J, Woods R, Sezer S and Turner R (2001). Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead, Journal of VLSI Signal Processing Systems, 28:1-2, (97-113), Online publication date: 1-May-2001.

Fridman J and Manolakos E (2001). Distributed Memory Parallel Architecture Based on Modular Linear Arrays for 2-D Separable Transforms Computation, Journal of VLSI Signal Processing Systems, 28:3, (187-203), Online publication date: 1-Jul-2001.

Kwai D and Parhami B (2001). Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization, Journal of VLSI Signal Processing Systems, 28:3, (235-243), Online publication date: 1-Jul-2001.

Kittitornkun S and Hu Y (2001). Efficient implementation of nested-loop multimedia algorithms, EURASIP Journal on Advances in Signal Processing, 2001:1, (129-146), Online publication date: 1-Jan-2001.

Wu C, Hong J and Wu C RSA cryptosystem design based on the Chinese remainder theorem Proceedings of the 2001 Asia and South Pacific Design Automation Conference, (391-395)

Das B and Banerjee S A CORDIC based array architecture for complex discrete wavelet transform Proceedings of the 11th Great Lakes symposium on VLSI, (79-84)

Singh A, Mukherjee A and Marek-Sadowska M Interconnect pipelining in a throughput-intensive FPGA architecture Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, (153-160)

Youn H, Oh C, Choo H, Chung J and Lee D (2001). An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship, IEEE Transactions on Computers, 50:4, (371-383), Online publication date: 1-Apr-2001.

Ahmed N, Mateev N and Pingali K (2001). Synthesizing Transformations for Locality Enhancement of Imperfectly-Nested Loop Nests, International Journal of Parallel Programming, 29:5, (493-544), Online publication date: 1-Oct-2001.

Fimmel D and Merker R (2001). Design of Processor Arrays for Reconfigurable Architectures, The Journal of Supercomputing, 19:1, (41-56), Online publication date: 1-May-2001.

Antola A and Breveglieri L (2000). Dedicated Circuits for the Generation of Windows in Image Processing Architectures, Journal of VLSI Signal Processing Systems, 25:1, (55-78), Online publication date: 1-May-2000.

Sarkar P (2000). A brief history of cellular automata, ACM Computing Surveys, 32:1, (80-107), Online publication date: 1-Mar-2000.

Wang C and Guo J (2000). New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m), IEEE Transactions on Computers, 49:10, (1120-1125), Online publication date: 1-Oct-2000.

Hong J and Wu C Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem Proceedings of the 2000 Asia and South Pacific Design Automation Conference, (565-570)

Ganesan S and Vemuri R An integrated temporal partioning and partial reconfiguration technique for design latency improvement Proceedings of the conference on Design, automation and test in Europe, (320-325)

Ahmed N, Mateev N and Pingali K Synthesizing transformations for locality enhancement of imperfectly-nested loop nests Proceedings of the 14th international conference on Supercomputing, (141-152)

Kienhuis B, Rijpkema E and Deprettere E Compaan Proceedings of the eighth international workshop on Hardware/software codesign, (13-17)

Singh A, Macchiarulo L, Mukherjee A and Marek-Sadowska M A novel high throughput reconfigurable FPGA architecture Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, (22-29)

Lim H, Piuri V and Swartzlander E (2000). A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms, IEEE Transactions on Computers, 49:12, (1297-1309), Online publication date: 1-Dec-2000.

Chatterjee M, Banerjee S and Pradhan D (2000). Buffer Assignment Algorithms on Data Driven ASICs, IEEE Transactions on Computers, 49:1, (16-32), Online publication date: 1-Jan-2000.

Ramanathan S, Visvanathan V and Nandy S (1999). Architectural Synthesis of Computational Engines for Subband Adaptive Filtering, Journal of VLSI Signal Processing Systems, 22:3, (173-195), Online publication date: 1-Sep-1999.

Lee S, Kim H, Kim J, Kim T and Yoo K Efficient fixed-size systolic arrays for the modular multiplication Proceedings of the 5th annual international conference on Computing and combinatorics, (442-451)

Parhami B and Kwai D (1999). Data-Driven Control Scheme for Linear Arrays, IEEE Transactions on Parallel and Distributed Systems, 10:1, (23-28), Online publication date: 1-Jan-1999.

Marino F and Swartzlander E (1999). Parallel Implementation of Multidimensional Transforms without Interprocessor Communication, IEEE Transactions on Computers, 48:9, (951-961), Online publication date: 1-Sep-1999.

Ke J and Tsay J (1999). An Approach to Checking Link Conflicts in the Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays, IEEE Transactions on Computers, 48:7, (732-737), Online publication date: 1-Jul-1999.

Liu C, Lu C and Hang K (1999). A Systolic Array Implementation of the Feng-Rao Algorithm, IEEE Transactions on Computers, 48:7, (690-706), Online publication date: 1-Jul-1999.

Narasimhan R, Rosenkrantz D and Ravi S (1999). Using Data Flow Information to Obtain Efficient Check Sets for Algorithm-Based Fault Tolerance, International Journal of Parallel Programming, 27:4, (289-323), Online publication date: 1-Aug-1999.

Kuhn P (1999). Fast MPEG-4 Motion Estimation, Journal of VLSI Signal Processing Systems, 23:1, (67-92), Online publication date: 1-Oct-1999.

Kyriakis-Bitzaros E and Goutis C (1999). A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays, Journal of VLSI Signal Processing Systems, 22:3, (151-162), Online publication date: 1-Sep-1999.

Likhoded N, Sobolevskii P and Tiunchik A (2023). Localization of edges in graph models of two-level algorithms, Cybernetics and Systems Analysis, 35:6, (895-902), Online publication date: 1-Nov-1999.

Chen Y and Kung S (1998). A Systolic Design Methodology with Application toFull-Search Block-Matching Architectures, Journal of VLSI Signal Processing Systems, 19:1, (51-77), Online publication date: 1-May-1998.

Chen Y and Kung S (1998). A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures, Journal of VLSI Signal Processing Systems, 19:1, (51-77), Online publication date: 1-May-1998.

Barlas G (1998). Collection-Aware Optimum Sequencing of Operations and Closed-Form Solutions for the Distribution of a Divisible Load on Arbitrary Processor Trees, IEEE Transactions on Parallel and Distributed Systems, 9:5, (429-441), Online publication date: 1-May-1998.

Guo J and Wang C (1998). Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF (2m), IEEE Transactions on Computers, 47:10, (1161-1167), Online publication date: 1-Oct-1998.

Zimmermann K and Achtziger W (1998). On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming, Journal of VLSI Signal Processing Systems, 19:1, (19-38), Online publication date: 1-May-1998.

Lee C and Lu M (1997). An Efficient VLSI Architecture for Full-Search Block Matching Algorithms, Journal of VLSI Signal Processing Systems, 15:3, (275-282), Online publication date: 1-Mar-1997.

Lee C and Lu M (1997). An Efficient VLSI Architecture for Full-Search Block MatchingAlgorithms, Journal of VLSI Signal Processing Systems, 15:3, (275-282), Online publication date: 1-Mar-1997.

Trainor D, Woods R and Mccanny J (1997). Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS", Journal of VLSI Signal Processing Systems, 16:1, (41-55), Online publication date: 1-May-1997.

Trainor D, Woods R and McCanny J (1997). Architectural Synthesis of Digital Signal ProcessingAlgorithms Using “IRIS”, Journal of VLSI Signal Processing Systems, 16:1, (41-55), Online publication date: 1-May-1997.

Pirsch P and Stolberg H Architectural approaches for video compression Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors

Rijpkema E, Hekstra G, Deprettere E and Ma J A strategy for determining a Jacobi specific dataflow processor Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors

Yeh Y and Lee C Buffer size optimization for full-search block matching algorithms Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors

Barua R and Sengupta S Architectures for Arithmetic over GF(2^m) Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

P. S and Prabhu K Novel CORDIC-Based Systolic Arrays for the DFT and the DHT Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97

Dutt S and Mahapatra N (1997). Node-covering, Error-correcting Codes and Multiprocessors with Very High Average Fault Tolerance, IEEE Transactions on Computers, 46:9, (997-1015), Online publication date: 1-Sep-1997.

Tao D (1997). A Self-Testing Nonincreasing Order Checker, IEEE Transactions on Computers, 46:7, (817-820), Online publication date: 1-Jul-1997.

Chiper D A New Systolic Array Algorithm for Memory-Based VLSI Array Implementation of DCT Proceedings of the 2nd IEEE Symposium on Computers and Communications (ISCC '97)

Jensen D, Madsen J and Pedersen S The importance of interfaces Proceedings of the 5th International Workshop on Hardware/Software Co-Design

Ozimek I, Verlic R and Tasic J Optimal Scheduling for Fast Systolic Array Implementations Proceedings of the 1997 European conference on Design and Test

Lee H, Lee J and Byun H Comparisons of fast 2D-DCT algorithms for parallel programmable digital signal processors Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97

Vajracharya S and Grunwald D Loop re-ordering and pre-fetching at run-time Proceedings of the 1997 ACM/IEEE conference on Supercomputing, (1-13)

Fridman J and Manolakos E (1997). On the Scalability of 2-D Discrete Wavelet Transform Algorithms, Multidimensional Systems and Signal Processing, 8:1-2, (185-217), Online publication date: 14-Feb-1997.

Mertzios B and Venetsanopoulos A (1997). Fast Implementation of 3-D Digital Filters Via SystolicArray Processors, Multidimensional Systems and Signal Processing, 8:3, (335-349), Online publication date: 1-Jul-1997.

Zimmermann K and Achtziger W (1997). Finding Space-Time Transformations for Uniform Recurrences viaBranching Parametric Linear Programming, Journal of VLSI Signal Processing Systems, 15:3, (259-274), Online publication date: 1-Mar-1997.

Sung J and Redinbo G (1996). Algorithm-Based Fault Tolerant Synthesis for Linear Operations, IEEE Transactions on Computers, 45:4, (425-438), Online publication date: 1-Apr-1996.

Sheliga M, Passos N and S' ha E Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications Proceedings of the 4th International Workshop on Hardware/Software Co-Design

Kodukula I and Pingali K Transformations for imperfectly nested loops Proceedings of the 1996 ACM/IEEE conference on Supercomputing, (12-es)

Lalgudi K, Papaefthymiou M and Potkonjak M Optimizing systems for effective block-processing Proceedings of the 33rd annual Design Automation Conference, (714-719)

Passos N and Sha E (1996). Achieving Full Parallelism Using Multidimensional Retiming, IEEE Transactions on Parallel and Distributed Systems, 7:11, (1150-1163), Online publication date: 1-Nov-1996.

Rim M and Jain R (1996). Valid Transformations, IEEE Transactions on Parallel and Distributed Systems, 7:4, (399-410), Online publication date: 1-Apr-1996.

Wang Q, Passos N and Sha E (1996). Optimal Data Scheduling for Uniform Multidimensional Applications, IEEE Transactions on Computers, 45:12, (1439-1444), Online publication date: 1-Dec-1996.

Sastry R, Ranganathan N and Jain R (1995). VLSI Architectures for High-Speed Range Estimation, IEEE Transactions on Pattern Analysis and Machine Intelligence, 17:9, (894-899), Online publication date: 1-Sep-1995.

Chang P and Tsay J (1995). Design of Space-Optimal Regular Arrays for Algorithms with Linear Schedules, IEEE Transactions on Computers, 44:5, (683-694), Online publication date: 1-May-1995.

Passos N, Sha E and Chao L Optimizing synchronous systems for multi-dimensional applications Proceedings of the 1995 European conference on Design and Test

Chen X and Megson G (1995). A General Methodology of Partitioning and Mapping for Given Regular Arrays, IEEE Transactions on Parallel and Distributed Systems, 6:10, (1100-1107), Online publication date: 1-Oct-1995.

Tsay J and Chang P (1995). Some New Designs of 2-D Array for Matrix Multiplication and Transitive Closure, IEEE Transactions on Parallel and Distributed Systems, 6:4, (351-362), Online publication date: 1-Apr-1995.

Tsay J and Chang P (1995). Design of Efficient Regular Arrays for Matrix Multiplication by Two-Step Regularization, IEEE Transactions on Parallel and Distributed Systems, 6:2, (215-222), Online publication date: 1-Feb-1995.

Luk W and Wu T Towards a declarative framework for hardware-software codesign Proceedings of the 3rd international workshop on Hardware/software co-design, (181-188)

Karpovsky M, Levitin L and Vainstein F (1994). Diagnosis by Signature Analysis of Test Responses, IEEE Transactions on Computers, 43:2, (141-152), Online publication date: 1-Feb-1994.

Wang Y, Chung P and Fuchs W (1994). Scheduling for Periodic Concurrent Error Detection in Processor Arrays, Journal of Parallel and Distributed Computing, 23:3, (306-313), Online publication date: 1-Dec-1994.

Jeang Y, Hsu Y, Wang J and Lee J High throughput pipelined data path synthesis by conserving the regularity of nested loops Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, (450-453)

Frick P and Stech D (1993). Epsilon-ritz method for solving optimal control problems, Journal of Optimization Theory and Applications, 79:1, (31-58), Online publication date: 1-Oct-1993.

Lee E Mulitdimensional Streams Rooted in Dataflow Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, (295-306)

Vasell J A partial evaluator for data flow graphs Proceedings of the 1993 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation, (206-215)

Gerasoulis A and Yang T (1993). On the Granularity and Clustering of Directed Acyclic Task Graphs, IEEE Transactions on Parallel and Distributed Systems, 4:6, (686-701), Online publication date: 1-Jun-1993.

Vinnakota B and Jha N (1993). Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs, IEEE Transactions on Parallel and Distributed Systems, 4:8, (864-874), Online publication date: 1-Aug-1993.

Wang C and Lin J (1993). A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/), IEEE Transactions on Computers, 42:9, (1141-1146), Online publication date: 1-Sep-1993.

Sun K and Fu H (1993). A Hybrid Neural Network Model for Solving Optimization Problems, IEEE Transactions on Computers, 42:2, (218-227), Online publication date: 1-Feb-1993.

Spray A and Jones S (1993). Performance Tradeoffs in Rings of Data-Driven Elements, IEEE Transactions on Computers, 42:1, (113-118), Online publication date: 1-Jan-1993.

Van Aelten F, Liao S, Allen J and Devadas S Automatic generation and verification of sufficient correctness properties for synchronous processors Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, (183-187)

Sarkar D and Mukherjee A (1992). Design of Optimal Systolic Algorithms for the Transitive Closure Problem, IEEE Transactions on Computers, 41:4, (508-512), Online publication date: 1-Apr-1992.

Bombana M, Buonanno G, Cavalloro P, Sciuto D and Zaza G A multi level testability assistant for VLSI design Proceedings of the conference on European design automation, (258-263)

Jin L and Yang L Parallel solution of Hough transform and convolution problems—a novel multimodal approach Proceedings of the 1992 ACM/SIGAPP symposium on Applied computing: technological challenges of the 1990's, (775-781)

Zapata E and Argüello F (1992). A VLSI Constant Geometry Architecture for the Fast Hartley and Fourier Transforms, IEEE Transactions on Parallel and Distributed Systems, 3:1, (58-70), Online publication date: 1-Jan-1992.

Skavantzos A and Stouraitis T (1992). Decomposition of Complex Multipliers Using Polynomial Encoding, IEEE Transactions on Computers, 41:10, (1331-1333), Online publication date: 1-Oct-1992.

Rutan A Advances in computer simulation Proceedings of the 24th annual symposium on Simulation, (2-7)

Hu X, Harber R and Bass S Minimizing the number of delay buffers in the synchronization of pipelined systems Proceedings of the 28th ACM/IEEE Design Automation Conference, (758-763)

Yang T and Gerasoulis A A fast static scheduling algorithm for DAGs on an unbounded number of processors Proceedings of the 1991 ACM/IEEE conference on Supercomputing, (633-642)

Lisper B (1991). Detecting static algorithms by partial evaluation, ACM SIGPLAN Notices, 26:9, (31-42), Online publication date: 1-Sep-1991.

Lisper B Detecting static algorithms by partial evaluation Proceedings of the 1991 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation, (31-42)

Chow E, Peterson J, Waterman M, Hunkapiller T and Zimmermann B A systolic array processor for biological information signal processing Proceedings of the 5th international conference on Supercomputing, (216-223)

Rutan A (1991). Advances in computer simulation, ACM SIGSIM Simulation Digest, 21:3, (2-7), Online publication date: 1-Apr-1991.

Lee E (1991). Consistency in Dataflow Graphs, IEEE Transactions on Parallel and Distributed Systems, 2:2, (223-235), Online publication date: 1-Apr-1991.

Shang W and Fortes J (1991). Time Optimal Linear Schedules for Algorithms with Uniform Dependencies, IEEE Transactions on Computers, 40:6, (723-742), Online publication date: 1-Jun-1991.

Wang L and Mendel J (1991). Three-Dimensional Structured Networks for Matrix Equation Solving, IEEE Transactions on Computers, 40:12, (1337-1346), Online publication date: 1-Dec-1991.

Roychowdhury V and Kailath T Study of parallelism in regular iterative algorithms Proceedings of the second annual ACM symposium on Parallel algorithms and architectures, (367-376)

Jayasinghe J and Herrmann O Two-level pipelining of systolic array graphics engines Proceedings of the Fourth Eurographics conference on Advances in Computer Graphics Hardware, (133-148)

Lenders P, Schröder H and Strazdins P (1989). Microprogramming instruction systolic arrays, ACM SIGMICRO Newsletter, 20:3, (56-69), Online publication date: 1-Aug-1989.

Lenders P, Schröder H and Strazdins P Microprogramming instruction systolic arrays Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture, (56-69)

Kim K and Prasanna-Kumar V (1989). Perfect Latin squares and parallel array access, ACM SIGARCH Computer Architecture News, 17:3, (372-379), Online publication date: 1-Jun-1989.

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