- Authors:
- James Reinders,
- James Jeffers
High Performance Parallelism Pearls shows how to leverage parallelism on processors and coprocessors with the same programming - illustrating the most effective ways to better tap the computational potential of systems with Intel Xeon Phi coprocessors and Intel Xeon processors or other multicore processors. The book includes examples of successful programming efforts, drawn from across industries and domains such as chemistry, engineering, and environmental science. Each chapter in this edited work includes detailed explanations of the programming techniques used, while showing high performance results on both Intel Xeon Phi coprocessors and multicore processors. Learn from dozens of new examples and case studies illustrating "success stories" demonstrating not just the features of these powerful systems, but also how to leverage parallelism across these heterogeneous systems. Promotes consistent standards-based programming, showing in detail how to code for high performance on multicore processors and Intel Xeon PhiTExamples from multiple vertical domains illustrating parallel optimizations to modernize real-world codesSource code available for download to facilitate further exploration
Cited By
Jeannot E, Mansouri F and Mercier G A hierarchical model to manage hardware topology in MPI applications Proceedings of the 24th European MPI Users' Group Meeting, (1-11)- Zapletal J, Merta M and Mal L (2017). Boundary element quadrature schemes for multi- and many-core architectures, Computers & Mathematics with Applications, 74:1, (157-173), Online publication date: 1-Jul-2017.
- Rucci E, García C, Botella G, De Giusti A, Naiouf M and Prieto-Matías M (2015). An energy-aware performance analysis of SWIMM, Concurrency and Computation: Practice & Experience, 27:18, (5517-5537), Online publication date: 25-Dec-2015.
- Bailey M Fundamentals seminar ACM SIGGRAPH 2015 Courses, (1-129)
- Pirk H, Madden S and Stonebraker M By their fruits shall ye know them Proceedings of the 11th International Workshop on Data Management on New Hardware, (1-6)
