Skip header Section
Skip Bibliometrics Section
Low power design in deep submicron electronicsOctober 1997
- Editors:
- Wolfgang Nebel,
- Jean Mermet
Abstract
No abstract available.
Skip Table Of Content Section
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
chapter
Cited By
- Chen W, Jiang F, Zheng W and Zhang P A dynamic energy conservation scheme for clusters in computing centers Proceedings of the Second international conference on Embedded Software and Systems, (244-255)
- Lyuh C and Kim T (2003). High-level synthesis for low power based on network flow method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11:3, (364-375), Online publication date: 1-Jun-2003.
- Murugavel A and Ranganathan N A Game-Theoretic Approach for Binding in Behavioral Synthesis Proceedings of the 16th International Conference on VLSI Design
- Lyuh C, Kim T and Liu C An integrated data path optimization for low power based on network flow method Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (553-559)
- Manich S, Gabarró A, Lopez M, Figueras J, Girard P, Guiller L, Landrault C, Pravossoudovitch S, Teixeira P and Santos M (2019). Low Power BIST by Filtering Non-Detecting Vectors, Journal of Electronic Testing: Theory and Applications, 16:3, (193-202), Online publication date: 1-Jun-2000.
Farkas K, Flinn J, Back G, Grunwald D and Anderson J (2000). Quantifying the energy consumption of a pocket computer and a Java virtual machine, ACM SIGMETRICS Performance Evaluation Review, 28:1, (252-263), Online publication date: 1-Jun-2000.- Farkas K, Flinn J, Back G, Grunwald D and Anderson J Quantifying the energy consumption of a pocket computer and a Java virtual machine Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, (252-263)
- Gerstendörfer S and Wunderlich H (2019). Minimized Power Consumption for Scan-Based BIST, Journal of Electronic Testing: Theory and Applications, 16:3, (203-212), Online publication date: 1-Jun-2000.
- Chung E, Benini L, Bogiolo A and De Micheli G Dynamic power management for non-stationary service requests Proceedings of the conference on Design, automation and test in Europe, (18-es)
- Chung E, Benini L and De Micheli G Dynamic power management using adaptive learning tree Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, (274-279)
- Gerstendörfer S and Wunderlich H Minimized Power Consumption For Scan-Based Bist Proceedings of the 1999 IEEE International Test Conference
- Nannarelli A and Lang T Power-delay tradeoffs for radix-4 and radix-8 dividers Proceedings of the 1998 international symposium on Low power electronics and design, (109-111)
- Benini L, Hodgson R and Siegel P System-level power estimation and optimization Proceedings of the 1998 international symposium on Low power electronics and design, (173-178)
- Benini L, Bogliolo A, Cavallucci S and Riccó B Monitoring system activity for OS-directed dynamic power management Proceedings of the 1998 international symposium on Low power electronics and design, (185-190)
- Benini L, Bogliolo A and De Micheli G Dynamic power management of electronic systems Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, (696-702)
- Prihozhy A Asynchronous scheduling and allocation Proceedings of the conference on Design, automation and test in Europe, (963-964)
- Benini L, De Micheli G, Lioy A, Macii E, Odasso G and Poncino M Computational kernels and their application to sequential power optimization Proceedings of the 35th annual Design Automation Conference, (764-769)
- Paleologo G, Benini L, Bogliolo A and De Micheli G Policy optimization for dynamic power management Proceedings of the 35th annual Design Automation Conference, (182-187)
Index Terms
- Low power design in deep submicron electronics
Recommendations
Design and performance improvement of low power SRAM using deep submicron technology
AbstractStatic random-access memory (SRAM) is a form of random-access memory (RAM) that stores each bit using latching circuitry (flip–flop). Embedded SRAMs take up the majority of the die space, resulting in higher power consumption. Despite significant ...
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
VLSID '00: Proceedings of the 13th International Conference on VLSI DesignDue to the quadratic reduction in the switching power dissipation, lowering supply voltage is obviously one of the most effective ways to reduce power consumption. However, the performance will degrade. In order to satisfy the high performance ...
Computer-aided design and scaling of deep submicron CMOS
A simulation tool-box and its applications to computer-aided design and scaling of deep-submicron CMOS are presented. The simulation tools are grouped around a mixed level approach and cover a wide range of applications. Due to the mixed-level approach, ...