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PA-RISC 2.0 architectureJanuary 1996
- Author:
- Gerry Kane
Abstract
No abstract available.
Cited By
Lozano R and Schulte C (2019). Survey on Combinatorial Register Allocation and Instruction Scheduling, ACM Computing Surveys, 52:3, (1-50), Online publication date: 31-May-2020.- Fu R, Lu J, Zhai A and Hsu W A study of the performance potential for dynamic instruction hints selection Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture, (67-80)
- Lee R and Fiskiran A (2018). PLX, Journal of VLSI Signal Processing Systems, 40:1, (85-108), Online publication date: 1-May-2005.
- Feng T, Jin B, Wang J, Park N, Kim Y and Lombardi F Fault tolerant clockless wave pipeline design Proceedings of the 1st conference on Computing frontiers, (350-356)
- Muchnick S and Gibbons P (2004). Efficient instruction scheduling for a pipelined architecture, ACM SIGPLAN Notices, 39:4, (167-174), Online publication date: 1-Apr-2004.
- Takeuchi M, Komatsu H and Nakatani T A new speculation technique to optimize floating-point performance while preserving bit-by-bit reproducibility Proceedings of the 17th annual international conference on Supercomputing, (305-315)
- Yang C, Sano B and Lebeck A (2000). Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions, IEEE Transactions on Computers, 49:9, (934-946), Online publication date: 1-Sep-2000.
- Zhang C and McKee S Hardware-only stream prefetching and dynamic access ordering Proceedings of the 14th international conference on Supercomputing, (167-175)
- Corella F A fast implementation of DES and triple-DES on PA-RISC 2.0 Proceedings of the 1st conference on Industrial Experiences with Systems Software - Volume 1, (12-12)
- Ghughal R, Mokkedem A, Nalumasu R and Gopalakrishnan G Using “test model-checking” to verify the Runway-PA8000 memory model Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures, (231-239)
- Swanson M, Stoller L and Carter J Increasing TLB reach using superpages backed by shadow memory Proceedings of the 25th annual international symposium on Computer architecture, (204-213)
- Swanson M, Stoller L and Carter J (1998). Increasing TLB reach using superpages backed by shadow memory, ACM SIGARCH Computer Architecture News, 26:3, (204-213), Online publication date: 1-Jun-1998.
- Pollard N and May D Using interval arithmetic the calculate data sizes for compilation to multimedia instruction sets Proceedings of the sixth ACM international conference on Multimedia, (279-284)
- Le B (2019). An out-of-order execution technique for runtime binary translators, ACM SIGPLAN Notices, 33:11, (151-158), Online publication date: 1-Nov-1998.
- Le B An out-of-order execution technique for runtime binary translators Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, (151-158)
- Le B (1998). An out-of-order execution technique for runtime binary translators, ACM SIGOPS Operating Systems Review, 32:5, (151-158), Online publication date: 1-Dec-1998.
- Yang C, Sano B and Lebeck A Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, (14-24)
- Santhanam V, Gornish E and Hsu W Data prefetching on the HP PA-8000 Proceedings of the 24th annual international symposium on Computer architecture, (264-273)
- Santhanam V, Gornish E and Hsu W (1997). Data prefetching on the HP PA-8000, ACM SIGARCH Computer Architecture News, 25:2, (264-273), Online publication date: 1-May-1997.
- Dunn D and Hsu W Instruction scheduling for the HP PA-8000 Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, (298-307)
- Lee R (1996). Subword Parallelism with MAX-2, IEEE Micro, 16:4, (51-59), Online publication date: 1-Aug-1996.
Index Terms
- PA-RISC 2.0 architecture
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