Browse Theses

A parallel vector processor (PVP) supercomputer relies on parallel processing and pipelines to deliver its enormous computational rate. Loop parallelization and vectorization together enable the performance of application programs to approach the theoretical peak rate of a PVP. This dissertation presents a series of powerful compiling techniques that broaden the classes of loops that can be vectorized and parallelized.

A serial loop can be executed in parallel by different processors if it does not have any loop-carried dependencies (LCD). We propose analysis and transformation techniques to detect and/or remove non-inherent LCD which include: geometric dependence testing methods to perform private array analysis, a code generation method to enable DOALL transformation of loops involving conditionally defined privatized variables, a symbolic analysis technique which in the presence of control constructs allows a compiler to remove false dependencies from irrelevant flow paths.

Loop vectorization has been found to be one of the most significant forms of parallelism. However, it has traditionally been limited to innermost loops and outer loops which are made innermost by the application of loop distribution and interchange. We propose a framework for direct vectorization of outer loops (OLV); i.e., vectorization of an outer loop without interchange or distribution. The framework includes: general vector execution modeling, legality of OLV, vector loop selection and an OLV vector code generator.

These techniques have been implemented in the Cray Fortran-90 compiling system. Implementation details are presented. The efficacy of these techniques are demonstrated by significant performance improvement of application programs.