- Authors:
- Abbas Sheibanyrad,
- Frdric Ptrot,
- Axel Jantsch
This book presents the research challenges that are due to the introduction of the 3rd dimension in chips for researchers and covers the whole architectural design approach for 3D-SoCs. Nowadays the 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures are emerging as interesting, truly hot, broad topics. The present book gathers the recent advances in the whole domain by renowned experts in the field to build a comprehensive and consistent book around the hot topics of three-dimensional architectures and micro-architectures. This book includes contributions from high level international teams working in this field.
Cited By
- Kagami T, Matsutani H, Koibuchi M, Take Y, Kuroda T and Amano H (2016). Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24:2, (493-506), Online publication date: 1-Feb-2016.
- Salamat R, Khayambashi M, Ebrahimi M and Bagherzadeh N (2016). A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs, IEEE Transactions on Computers, 65:11, (3265-3279), Online publication date: 1-Nov-2016.
Bahrebar P and Stroobandt D Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip Proceedings of the 8th International Workshop on Network on Chip Architectures, (15-20)- Furhad M and Kim J (2014). A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures, The Journal of Supercomputing, 69:2, (766-792), Online publication date: 1-Aug-2014.
- Diguet J, Strum M, Le Griguer N, Caetano L and Sepúlveda M Scalable NoC-based architecture of neural coding for new efficient associative memories Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, (1-9)
- Dutoit D, Guthmuller E and Miro-Panades I 3D integration for power-efficient computing Proceedings of the Conference on Design, Automation and Test in Europe, (779-784)
- Sepúlveda M, Gogniat G, Sepúlveda D, Pires R, Chau W and Strum M 3DMIA Proceedings of the 15th annual conference companion on Genetic and evolutionary computation, (167-168)
- Foroutan S, Sheibanyrad A and Pétrot F Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces Proceedings of the 49th Annual Design Automation Conference, (366-375)
- Matsutani H, Take Y, Sasaki D, Kimura M, Ono Y, Nishiyama Y, Koibuchi M, Kuroda T and Amano H A vertical bubble flow network using inductive-coupling for 3-D CMPs Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (49-56)
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