- Author:
- Suntae Hwang
Recently, it has been recognized that logic testing does not detect many physical defects such as bridging and open faults. In this study, we examine the effectiveness of combined logic and Iddq testing to detect stuck-at and bridging faults. The stuck-at faults are detected by logic testing by voltage measurement and Iddq testing detects bridging faults.
Near-minimal stuck-at test sets are used for this combined logic and Iddq test environment. These near-minimal stuck-at test sets are generated using standard test programs, while using collapsed fault lists. We examined ISCAS '85 and ISCAS '89 benchmark circuits. A comparison is given for the fault coverage obtained under this combined test environment with other studies based on pure logic test and Iddq test. Also, the results of Iddq-based test sets (vectors generated specifically for Iddq testing) are compared with those of stuck-at test sets. To save the test effort, we also examine the bridging fault coverage in Iddq testing when partial stuck-at test sets are used. We present a case study on a microprogrammed processor using a functional test set in the combined test environment to detect logic and bridging faults.
Based upon results obtained during this study, we established a relationship between stuck-at test sets and bridging fault coverage in Iddq testing, and finally, we suggest a guideline on the use of stuck-at test sets in Iddq environment.
Index Terms
- VLSI testing for high reliability: mixing IDDQ and logic testing
Recommendations
Testing High Speed VLSI Devices Using Slower Testers
VTS '99: Proceedings of the 1999 17TH IEEE VLSI Test SymposiumThe speed of new VLSI designs is rapidly increasing. Assuring the performance of the circuit requires that the circuit be tested at its intended operating speed. The high cost of high speed testers makes it impossible for the testers to follow the ...
VLSI testing and test power
IGCC '11: Proceedings of the 2011 International Green Computing Conference and WorkshopsThis paper first reviews the basics of VLSI testing, focusing on test generation and design for testability. Then it discusses the impact of test power in scan testing, and highlights the need for low-power VLSI testing.
Current status and future trend on CAD tools for VLSI testing
ATS '00: Proceedings of the 9th Asian Test SymposiumFor current VLSI designs, there are two kinds of well-accepted digital testing technologies. One is for embedded memories and the other is for the logic. For embedded memories, Built-In-Self-Test (BIST) is used. For the logic, the main solutions are ...