We report on our experience with the hardware transactional memory (HTM) feature of two revisions of a prototype multicore processor. Our experience includes a number of promising results using HTM to improve performance in a variety of contexts, and also identifies some ways in which the feature could be improved to make it even better. We give detailed accounts of our experiences, sharing techniques we used to achieve the results we have, as well as describing challenges we faced in doing so. This technical report expands on our ASPLOS paper [9], providing more detail and reporting on additional work conducted since that paper was written.
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Dice D, Herlihy M and Kogan A (2018). Improving Parallelism in Hardware Transactional Memory, ACM Transactions on Architecture and Code Optimization, 15:1, (1-24), Online publication date: 2-Apr-2018.- Dice D, Kogan A and Lev Y Refined transactional lock elision Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, (1-12)
- Brown T, Kogan A, Lev Y and Luchangco V Investigating the Performance of Hardware Transactions on a Multi-Socket Machine Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures, (121-132)
- Dice D, Kogan A and Lev Y (2016). Refined transactional lock elision, ACM SIGPLAN Notices, 51:8, (1-12), Online publication date: 9-Nov-2016.
- Dice D, Kogan A, Lev Y, Merrifield T and Moir M Adaptive integration of hardware and software lock elision techniques Proceedings of the 26th ACM symposium on Parallelism in algorithms and architectures, (188-197)
- Dice D, Lev Y, Liu Y, Luchangco V and Moir M Using hardware transactional memory to correct and simplify and readers-writer lock algorithm Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming, (261-270)
- Dice D, Lev Y, Liu Y, Luchangco V and Moir M (2013). Using hardware transactional memory to correct and simplify and readers-writer lock algorithm, ACM SIGPLAN Notices, 48:8, (261-270), Online publication date: 23-Aug-2013.
- Dalessandro L, Carouge F, White S, Lev Y, Moir M, Scott M and Spear M Hybrid NOrec Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems, (39-52)
- Dalessandro L, Carouge F, White S, Lev Y, Moir M, Scott M and Spear M (2011). Hybrid NOrec, ACM SIGARCH Computer Architecture News, 39:1, (39-52), Online publication date: 17-Mar-2011.
- Dalessandro L, Carouge F, White S, Lev Y, Moir M, Scott M and Spear M (2011). Hybrid NOrec, ACM SIGPLAN Notices, 46:3, (39-52), Online publication date: 17-Mar-2011.
- Dragojević A, Herlihy M, Lev Y and Moir M On the power of hardware transactional memory to simplify memory management Proceedings of the 30th annual ACM SIGACT-SIGOPS symposium on Principles of distributed computing, (99-108)
- Moir M and Nussbaum D What kinds of applications can benefit from transactional memory? Proceedings of the 2010 international conference on Computer Architecture, (150-160)
- Dice D, Lev Y, Marathe V, Moir M, Nussbaum D and Olszewski M Simplifying concurrent algorithms by exploiting hardware transactional memory Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures, (325-334)
- Tabba F (2010). Adding concurrency in python using a commercial processor's hardware transactional memory support, ACM SIGARCH Computer Architecture News, 38:5, (12-19), Online publication date: 29-Dec-2011.
- Dice D, Lev Y, Moir M and Nussbaum D Early experience with a commercial hardware transactional memory implementation Proceedings of the 14th international conference on Architectural support for programming languages and operating systems, (157-168)
- Dice D, Lev Y, Moir M and Nussbaum D (2009). Early experience with a commercial hardware transactional memory implementation, ACM SIGPLAN Notices, 44:3, (157-168), Online publication date: 28-Feb-2009.
- Tabba F, Moir M, Goodman J, Hay A and Wang C NZTM Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures, (204-213)
- Dice D, Lev Y, Moir M and Nussbaum D (2009). Early experience with a commercial hardware transactional memory implementation, ACM SIGARCH Computer Architecture News, 37:1, (157-168), Online publication date: 1-Mar-2009.
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Early experience with a commercial hardware transactional memory implementation
ASPLOS XIV: Proceedings of the 14th international conference on Architectural support for programming languages and operating systemsWe report on our experience with the hardware transactional memory (HTM) feature of two pre-production revisions of a new commercial multicore processor. Our experience includes a number of promising results using HTM to improve performance in a variety ...
Early experience with a commercial hardware transactional memory implementation
ASPLOS 2009We report on our experience with the hardware transactional memory (HTM) feature of two pre-production revisions of a new commercial multicore processor. Our experience includes a number of promising results using HTM to improve performance in a variety ...
Early experience with a commercial hardware transactional memory implementation
ASPLOS 2009We report on our experience with the hardware transactional memory (HTM) feature of two pre-production revisions of a new commercial multicore processor. Our experience includes a number of promising results using HTM to improve performance in a variety ...