- Author:
- Joy Susan Shetler
The DART multiprocessor is an experimental computer system which uses a decoupled philosophy to maintain a high throughput, fine grained multithreading instruction execution. Multiple instruction streams execute in a decoupled pipeline allowing memory and I/O accesses to be overlapped with useful processing. Fault tolerance is built into the system within the DART interconnection network. This architecture is useful in systems implemented in high speed technologies, where substantial mismatches in pipeline to memory speed occur.Chapter 1 presents an introduction to the DART system and a discussion of related work. High speed technologies and some of the techniques used in DART to maximize system performance are discussed in Chapter 2. In Chapter 3, the interconnection network, functional units in the DART processor, and I/O processor is described. A picture of the environment and resources of an instruction stream during execution is presented in Chapter 4. A description of the internal hardware design of the functional units in the DART processor is given in Chapter 5. Chapter 6 presents simulation results for several DART systems. Simulations from three different processor models show the effects that changes in the instruction execution models, data placement, and number of registers have on the performance. Finally, future directions for the DART system development are discussed in Chapter 7.
Index Terms
- DART: a decoupled computer architecture
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