Design of an ASIP architecture for low-level visual elaborations

We consider the design process of VLSI systems dedicated to the real-time implementation of cooperative algorithms whose functionalities can be characterized by multilayer ensembles of simple elements which interact locally. These algorithms are related, even though not exclusively, to the implementation of various tasks in low-level machine vision. The starting point in the design process is the formulation of the sequential algorithm that computes the behavior of the system. Algorithmic transformations are performed to expose the parallelism originally present in the task. Given the description in terms of parallel loops, we partition the system and organize it as a set of processing units. The architectural structure of these units takes properly into account the algorithmic constraints on precision both in data representation and computation. The program flow implemented by our programmable architectural solution (ASIP) is an iterative sequence of multiply-and-accumulate operations performed in parallel. The programmability concerns both the structure/coefficients of the algorithm-depending on the specific application-and its computational parameters. The architecture's main blocks are described in VHDL and synthesized as a semi-custom chip, using standard tools. Following this procedure, we designed an ASIP core for performing real-time texture-based image segregation.