Yi Zhao
Abstract
With processors and system-on-chips using nano-meter technologies, several design and test efforts have been recently developed to eliminate and test for many emerging DSM noise effects. In this paper, we show the emergence of multisource noise effects, where multiple DSM noise sources combine to produce functional and timing errors even when each separate noise source itself does not. We show the dynamic nature of multisource noise, and the need for online testing to detect such noise errors. We propose an online approach based on low-cost double-sampling data checking circuit to test for such noise effects in on-chip buses. Based on the proposed circuit, an effective and efficient testing methodology has been developed to facilitate online testing for generic on-chip buses. The applicability of this methodology is demonstrated through embedding the online detection circuit in a bus design. The validated design shows the effectiveness of the proposed testing methodology for multisource noise-induced errors in global interconnects and buses.
- {1} D. Sylvester and K. Keutzer, "A global wiring paradigm for deep submicron design," IEEE Trans. Computer-Aided Design, vol. 19, pp. 242-252, Feb. 2000. Google Scholar
Digital Library
- {2} L. Pileggi, "Coping with RC(L) interconnect design headaches," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1995, pp. 246-252. Google Scholar
- {3} M. A. Breuer and S. K. Gupta, "Process aggravated noise (PAN): New validation and test problems," in Proc. Int. Test Conf., 1996, pp. 914-923. Google ScholarCross Ref
- {4} A. Deutsch, G. Kopcsay, P. Restle, H. Smith, G. Katopis, W. Becker, P. Coteus, C. Surovic, B. Rubin, R. Dunne, T. Gallo, K. Jenkins, L. Terman, R. Dennard, G. Sai-Halasz, B. Krauter, and D. Knebel, "When are transmission-line effects important for on-chip interconnections?," IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997.Google ScholarCross Ref
- {5} P. Nordholz, D. Treytnar, J. Otterstedt, H. Grabinski, D. Niggemeyer, and T. W. Williams, "Signal integrity problems in deep submicron arising from interconnects between cores," in Proc. IEEE VLSI Test Symp., 1998, pp. 28-33. Google Scholar
- {6} M. Graziano, G. Masera, G. Piccini, and M. Zamboni, "Power supply designs for switching-noise control in deep-submicron circuits design flows," Analog Integrated Circuits Signal Processing, vol. 31, no. 3, pp. 225-248, 2002. Google ScholarDigital Library
- {7} J. L. Neves and E. G. Friedman, "Optimal clock skew scheduling tolerant to process variations," in Proc. 33rd Design Automation Conf., 1996, pp. 623-628. Google ScholarDigital Library
- {8} A. Balboni, C. Costi, M. Pellencin, A. Quadrini, and D. Sciuto, "Clock skew reduction in ASIC logic design: A Methodology for clock tree management," IEEE Trans. Computer-Aided Design, vol. 17, pp. 344-356, Apr. 1998. Google ScholarDigital Library
- {9} Y. Cao, C. Hu, X. Huang, A. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester, "Effects of global interconnect optimizations on performance estimation of deep submicron design," in Proc. Int. Conf. Computer-Aided Design, 2002, pp. 56-61. Google Scholar
- {10} W. Dally and J. Poulton, Digital Systems Engineering. Cambridge, U.K.: Cambridge Univ. Press, 1998. Google ScholarDigital Library
- {11} C. Metra, M. Favalli, and B. Ricco, "Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines," IEEE Trans. Computers, vol. 49, pp. 560-74, June 2000. Google ScholarDigital Library
- {12} M. Nicolaidis, "Time redundancy based soft-error tolerance to rescue nanometer technologies," in Proc. 17th IEEE VLSI Test Symp., 1999, pp. 89-94. Google Scholar
- {13} J. Gambles and K. J. Hass, "U.S. Patent," 6326809, 1999.Google Scholar
- {14} Y.I. Ismail, E. G. Friedman, and J. L. Neves, "Figures of merit to characterize the importance of on-chip inductance," IEEE Trans. VLSI Syst., vol. 7, pp. 442-449, June 1999. Google ScholarCross Ref
- {15} K. T. Lee, C. Nordquist, and J. A. Abraham, "Automatic test generation for crosstalk glitches in digital circuits," in Proc. 16th IEEE VLSI Test Symp., 1998, pp. 34-39. Google Scholar
- {16} W. Chen, S. K. Gupta, and M. A. Breuer, "Test generation in VLSI circuits for crosstalk noise," in Proc. IEEE Int. Test Conf., 1998, pp. 641-650. Google Scholar
- {17} M. Cuviello, S. Dey, X. Bai, and Y. Zhao, "Fault modeling and simulation for crosstalk in system-on-chip interconnects," in Proc. 1999 IEEE/ACM Int. Conf. Computer-Aided Design, 1999, pp. 297-303. Google ScholarDigital Library
- {18} Y. Jiang, T. Young, and K. T. Cheng, "VIP- an input pattern generator for identifying critical voltage drop for deep submicron designs," in Proc. 1999 Int. Symp. Low-Power Electronics Design, 1999, pp. 156-161. Google ScholarDigital Library
- {19} "National Technology Roadmap for Semiconductors," Semiconductor Industry Association, 1999.Google Scholar
- {20} Signal Integrity/Physical Verification Products of Simplex (ElectronStrom TM etc.,) at Company Website. {Online}. Available: http:// www.simplex.com/img/electronstorm.pdfGoogle Scholar
- {21} Signal Integrity/physical Verification Products of Cadence Corporation Company Website. {Online}. Available: http://www.cadence.com/products/sidigital.htmlGoogle Scholar
- {22} P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic," in Proc. 2002 Int. Conf. Dependable Systems and Networks, 2002, pp. 389-398. Google ScholarDigital Library
- {23} L. Anghel and M. Nicolaidis, "Cost reduction and evaluation of a temporary faults detecting technique," in Proc. Design, Automation Test Eur. Conf Exhibition 2000, 2000, pp. 591-598. Google Scholar
- {24} R. Rajsuman, System-on-a Chip: Design and Test. Norwood, MA: Artech House, 2000, p. 36. Google Scholar
- {25} R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, pp. 490-504, 2001.Google ScholarCross Ref
- {26} (2002)International Technology Roadmap for Semiconductor (ITRS) Updated Version. {Online}. Available: http://public.itrs.netGoogle Scholar
- {27} D. Velenis, K. T. Tang, L S. Kourtev, V. Adler, F. Baez, and E. G. Friedman, "Demonstration of speed enhancements on an industrial circuit through application of nonzero clock skew scheduling," in Proc. 8th Int. Conf. Electronics, Circuits, Systems, 2001, pp. 1021-1025.Google Scholar
- {28} Siemens AG, OMI 324 Draft Standard: PI-Bus Rev. 0.3d, 1994.Google Scholar
- {29} PI-Bus VHDL Toolkit version 3.1, Center for VLSI, Computer Graphics, Univ. of Sussex, Sussex, U.K., 1996.Google Scholar
Index Terms
- Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses
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