Zhiyuan Yan
ABSTRACT
Based on a new reformulation of the extended Euclidean algorithm, systolic architectures suitable for VLSI implementations are proposed for finite field inversion and division in this paper. The architectures proposed in this paper can achieve O(m2) area-time complexity, O(m) latency, and critical path delays of two logic gates. These architectures show improved performances when compared with previously proposed architectures.
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Index Terms
- High-speed systolic architectures for finite field inversion and division
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