William J. Dally
Brian Towles
ABSTRACT
Using on-chip interconnection networks in place of ad-hoc glo-bal wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
- 1."The CoreConnect TM Bus Architecture" IBM, 1999, http://www.chips.ibm.com/products/coreconnect/docs/crcon_wp.pdf.Google Scholar
- 2.DALLY,WILLIAM J., "Virtual Channel Flow Control." IEEE Transactions on Parallel and Distributed Systems, March 1992, pp. 194-205. Google ScholarDigital Library
- 3.DALLY,WILLIAM J., AND POULTON,JOHN W., Digital Systems Engineering, Cambridge University Press, 1998. Google ScholarDigital Library
- 4.MIZUNO,MASAYUKI AND DALLY,WILLIAM J., "Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data," 2001 ISSCC, February, 2001, pp. 346-347.Google Scholar
- 5."Open Core Protocol TM Data Sheet" Sonics, Inc., http://www.sonicsinc.com/Documents/OpenCoreProtocol_DS.pdf.Google Scholar
- 6.PEH,LI-SHIUAN AND DALLY,WILLIAM J., "A Delay Model and Speculative Architecture for Pipelined Routers." Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Jan. 2001, pp. 255-266. Google ScholarDigital Library
- 7.SEITZ,CHARLES, "Let's Route Packets Instead of Wires." Advanced Research in VLSI: Proceedings of the Sixth MIT Conference, 1990, pp. 133-138. Google ScholarDigital Library
- 8.VSI Alliance, http://www.vsi.org.Google Scholar
Index Terms
- Route packets, not wires: on-chip inteconnection networks
Recommendations
Replacing global wires with an on-chip network: a power analysis
ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and designThis paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and voltage scaling, to significantly reduce the energy to send a bit across chip. ...
NTHU-route 2.0: a robust global router for modern designs
This paper presents a robust global router called NTHU-Route 2.0 that improves the solution quality and runtime of NTHU-Route by the following enhancements: 1) a new history based cost function; 2) new ordering methods for congested region ...
Logic emulation with virtual wires
Logic emulation enables designers to functionally verify complex integrated circuits prior to chip fabrication. However, traditional FPGA-based logic emulators have poor inter-chip communication bandwidth, commonly limiting gate utilization to less than ...
Comments