- 1 A. H. BURKS, H. H. GOLDSTINE, AND J. vos NEUMANN, Preliminary discussion of the logical design of an electronic computing instrument, Institute for Advanced Study, Princeton, N. J., first edition June 1946, second edition 1947; Section 5.2. Also subsequent reports by H. H. Goldstine and J. yon Neumann.Google Scholar
- 2 See, for example, R. K. RICHARDS, Arithmetic Operations in Digital Computers, D. Van Nostrand, 1955; Chapter 1.Google Scholar
- 3 WM. D. BELL, A Management Guide to Electronic Computers, McGraw Hill, 1957; pp. 92-97.Google Scholar
- 4 C. E. SHANNON AND W. WEAVER, The Mathematical Theory of Communication, The University of Illinois Press, 1949. Google ScholarDigital Library
- 5 L. BRILLOUIN, Science and Information Theory, Academic Press, 1956; pp. 3-4.Google Scholar
- 6 F. P. BROOKS, JR., G. A. BLAAUW, AND W. BUCHHOLZ, Processing data in bits and pieces, IRE Transactions on Electronic Computers, EC-8, No. 2; June 1959.Google Scholar
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