Jared Stark
Supplemental Material
Available for Download
- 1.M. Butler and Y. Patt, An investigation of the performance of various dynamic scheduling techniques, in Proceedings of the 25th Annual ACM/IEEE International Symposium on Microarchitecture, 1992. Google Scholar
Digital Library
- 2.IA-32 Intel Architecture Software Developer's Manual With Preliminary Willamette Architecture Information Volume 1: Basic Architecture, Intel Corporation, 2000.Google Scholar
- 3.S. Palacharla, N. P. Jouppi, and J. E. Smith, Complexity-effective superscalar processors, in Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997. Google ScholarDigital Library
- 4.R. M. Tomasulo, An efficient algorithm for exploiting multiple arithmetic units, IBM Journal of Research and Development, vol. 11, pp. 2533, January 1967.Google ScholarDigital Library
- 5.K. C. Yeager, The MIPS R10000 superscalar microprocessor, IEEE Micro, vol. 16, no. 2, pp. 2841, April 1996. Google ScholarDigital Library
- 6.A. Yu, Client Architecture for the New Millennium, Intel Corporation, February 2000. Spring 2000 Intel Developer Forum Keynote Presentation.Google Scholar
Index Terms
- On pipelining dynamic instruction scheduling logic
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