Paolo Faraboschi
ABSTRACT
Lx is a scalable and customizable VLIW processor technology platform designed by Hewlett-Packard and STMicroelectronics that allows variations in instruction issue width, the number and capabilities of structures and the processor instruction set. For Lx we developed the architecture and software from the beginning to support both scalability (variable numbers of identical processing resources) and customizability (special purpose resources).
In this paper we consider the following issues. When is customization or scaling beneficial? How can one determine the right degree of customization or scaling for a particular application domain? What architectural compromises were made in the Lx project to contain the complexity inherent in a customizable and scalable processor family?
The experiments described in the paper show that specialization for an application domain is effective, yielding large gains in price/performance ratio. We also show how scaling machine resources scales performance, although not uniformly across all applications. Finally we show that customization on an application-by-application basis is today still very dangerous and much remains to be done for it to become a viable solution.
- 1.Colwell, R., O'Donnell, J., Papworth, D., and Rodman, P. "Instruction Storage Method with a Compressed Format using a Mask Word", U.S. Patent 5057837, Oct. 1991.Google Scholar
- 2.Colwell, R. P., Nix, R. P., O'Donnell, J. J., Papworth, D. B., and Rodman, P.K. A VLIW Architecture for a Trace Scheduling Compiler. In Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems, pages pages 180-192. ACM. 1987. Google ScholarCross Ref
- 3.Faraboschi, P., Fisher, J. and Desoli, G Clustered Instruction-Level Parallel Processors. Hewlett-Packard Technical Report. HPL-98-204, 1998.Google Scholar
- 4.Fisher, J., Faraboschi, P., and Desoli, G. "Custom-Fit Processors: Letting Applications Define Architectures". In Proc. 30th Annual International Symposium on Microarchitecture (MICRO30), Paris, France, December 1996. Google ScholarDigital Library
- 5.Fisher, J. "Trace Scheduling: A Technique for Global Microcode Compaction". IEEE Trans. on Computers, C- 30(7):478-490. 1981.Google ScholarDigital Library
- 6.IBM Corp. "CodePack Compression for PowerPC". Available as: http://www.chips.ibm.com/products/powerpc/ cores/cdpak.htmlGoogle Scholar
- 7.Lowney, P.G. et al. (1993). "The Multiflow Trace Scheduling Compiler". The Journal of Supercomputing, 7(1/2):51-142. Google ScholarDigital Library
- 8.Raik-Allen G. "ARC Cores rides platform divergence trend". Red Herring, June 1999. Available as http://www. redherring.com/insider/1999/0604/vcarccores.htmlGoogle Scholar
- 9.Rau B., Yen D., Yen W., and Towle R., "The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs," IEEE Computer, January 1989, pp. 12-35. Google ScholarDigital Library
- 10.Schneier B. "Applied Cryptography (Second Edition). Protocols, Algorithms and Source Code in C". John Wiley and Sons. 1996. Google ScholarDigital Library
- 11.Sharangpani H. "Intel~ Itanium Processor Microarchitecture Overview". Microprocessor Forum. 1999. Available as: http ://developer.intel.com/design/ia-64/architecture.htmGoogle Scholar
- 12.Slavenburg G, Rathnam S., Dijkstra H, "The TriMedia TM- 1 PCI VLIW Media Processor", Hot Chips 8, August 1996.Google Scholar
- 13.StarCore Alliance (Motorola Semiconductors and Lucent Technologies). Leadership in DSP Technology for Communications Applications. Available as: http://www. starcore-dsp.com/files/S C 140pres.pdfGoogle Scholar
- 14.Tensilica Inc., "Application Specific Microprocessor Solutions (Data Sheet for Xtensa V1)", 1998. Available as: http ://www.tensilica.com/datasheet.pdfGoogle Scholar
- 15.Texas Instruments Inc. "TMS320C6000: a High Performance DSP Platform". Available as: http://www.ti.com/ sc/docs/products/dsp/c6000/index.htmGoogle Scholar
- 16.Wolfe, A. and Chanin, A., "Executing Compressed Programs on An Embedded RISC Architecture", In Proceedings of the 25th Annual International Symposium on Microarchitecture, pages 81-91, Portland, Oregon Google ScholarDigital Library
Index Terms
- Lx: a technology platform for customizable VLIW embedded processing
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