An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS

ABSTRACT

A compact and low energy circuitry of time-based stochastic computing (TBSC) have been designed. In the TBSC theory, stochastic numbers (SNs) are represented by duty-cycle of periodic signals. Additionally, multiplication and addition operations of the SNs require the signals to be in-harmonic and uncorrelated in frequency. In order to dynamically tune the frequency, a current-starved structure is applied in a three-stage inverter chain type of oscillator with the neuron-MOS mechanism. By feeding the pulses to a neuron-MOS based inverter with adjustable switching threshold, arbitrary duty-cycle for representing any specific SNs can be generated with the accuracy of 96%. In this manner, the implementation cost of the stochastic number generator (SNG) is reduced by avoiding the use of complex frequency-programmable-oscillator and comparator which are exploited in the conventional TBSC circuit. From circuit simulation results, multiplication and addition operations can be retrieved by proposed TBCS circuits with the accuracy of about 97%. The entire circuitry utilizes 210 CMOS transistors, and consumes the energy of 2.5pJ for one computation, which is 14% and 36.7% of conventional TBCS circuit, respectively.

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Index Terms

• Computer systems organization

• Hardware

  • Integrated circuits

  • Very large scale integration design