Abstract
Innovations like domain-specific hardware, enhanced security, open instruction sets, and agile chip development will lead the way.
- Beck, K., Beedle, M., Van Bennekum, A., Cockburn, A., Cunningham, W., Fowler, M. ... and Kern, J. Manifesto for Agile Software Development, 2001; https://agilemanifesto.org/Google Scholar
- Bhandarkar, D. and Clark, D.W. Performance from architecture: Comparing a RISC and a CISC with similar hardware organization. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (Santa Clara, CA, Apr. 8--11). ACM Press, New York, 1991, 310--319. Google ScholarDigital Library
- Chaitin, G. et al. Register allocation via coloring. Computer Languages 6, 1 (Jan. 1981), 47--57. Google ScholarDigital Library
- Dally, W. et al. Hardware-enabled artificial intelligence. In Proceedings of the Symposia on VLSI Technology and Circuits (Honolulu, HI, June 18--22). IEEE Press, 2018, 3--6.Google Scholar
- Dennard, R. et al. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE Journal of Solid State Circuits 9, 5 (Oct. 1974), 256--268.Google ScholarCross Ref
- Emer, J. and Clark, D. A characterization of processor performance in the VAX-11/780. In Proceedings of the 11<sup>th</sup> International Symposium on Computer Architecture (Ann Arbor, MI, June). ACM Press, New York, 1984, 301--310. Google ScholarDigital Library
- Fisher, J. The VLIW machine: A multiprocessor for compiling scientific code. Computer 17, 7 (July 1984), 45--53. Google ScholarDigital Library
- Fitzpatrick, D.T., Foderaro, J.K., Katevenis, M.G., Landman, H.A., Patterson, D.A., Peek, J.B., Peshkess, Z., Séquin, C.H., Sherburne, R.W., and Van Dyke, K.S. A RISCy approach to VLSI. ACM SIGARCH Computer Architecture News 10, 1 (Jan. 1982), 28--32. Google ScholarDigital Library
- Flynn, M. Some computer organizations and their effectiveness. IEEE Transactions on Computers 21, 9 (Sept. 1972), 948--960. Google ScholarDigital Library
- Fowers, J. et al. A configurable cloud-scale DNN processor for real-time AI. In Proceedings of the 45<sup>th</sup> ACM/IEEE Annual International Symposium on Computer Architecture (Los Angeles, CA, June 2--6). IEEE, 2018, 1--14. Google ScholarDigital Library
- Hennessy, J. and Patterson, D. A New Golden Age for Computer Architecture. Turing Lecture delivered at the 45<sup>th</sup> ACM/IEEE Annual International Symposium on Computer Architecture (Los Angeles, CA, June 4, 2018); http://iscaconf.org/isca2018/turing_lecture.html; https://www.youtube.com/watch?v=3LVeEjsn8TsGoogle Scholar
- Hennessy, J., Jouppi, N., Przybylski, S., Rowen, C., Gross, T., Baskett, F., and Gill, J. MIPS: A microprocessor architecture. ACM SIGMICRO Newsletter 13, 4 (Oct. 5, 1982), 17--22. Google ScholarCross Ref
- Hennessy, J. and Patterson, D. Computer Architecture: A Quantitative Approach. Morgan Kauffman, San Francisco, CA, 1989. Google ScholarDigital Library
- Hill, M. A primer on the meltdown and Spectre hardware security design flaws and their important implications, Computer Architecture Today blog (Feb. 15, 2018); https://www.sigarch.org/a-primer-on-the-meltdown-spectre-hardware-security-design-flaws-and-their-important-implications/Google Scholar
- Hopkins, M. A critical look at IA-64: Massive resources, massive ILP, but can it deliver? Microprocessor Report 14, 2 (Feb. 7, 2000), 1--5.Google Scholar
- Horowitz M. Computing's energy problem (and what we can do about it). In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (San Francisco, CA, Feb. 9--13). IEEE Press, 2014, 10--14.Google Scholar
- Jouppi, N., Young, C., Patil, N., and Patterson, D. A domain-specific architecture for deep neural networks. Commun. ACM 61, 9 (Sept. 2018), 50--58. Google ScholarDigital Library
- Jouppi, N.P., Young, C., Patil, N., Patterson, D., Agrawal, G., Bajwa, R., Bates, S., Bhatia, S., Boden, N., Borchers, A., and Boyle, R. In-datacenter performance analysis of a tensor processing unit. In Proceedings of the 44<sup>th</sup> ACM/IEEE Annual International Symposium on Computer Architecture (Toronto, ON, Canada, June 24--28). IEEE Computer Society, 2017, 1--12. Google ScholarDigital Library
- Kloss, C. Nervana Engine Delivers Deep Learning at Ludicrous Speed. Intel blog, May 18, 2016; https://ai.intel.com/nervana-engine-delivers-deep-learning-at-ludicrous-speed/Google Scholar
- Knuth, D. The Art of Computer Programming: Fundamental Algorithms, First Edition. Addison Wesley, Reading, MA, 1968.Google Scholar
- Knuth, D. and Binstock, A. Interview with Donald Knuth. InformIT, Hoboken, NJ, 2010; http://www.informit.com/articles/article.aspxGoogle Scholar
- Kung, H. and Leiserson, C. Systolic arrays (for VLSI). Chapter in Sparse Matrix Proceedings Vol. 1. Society for Industrial and Applied Mathematics, Philadelphia, PA, 1979, 256--282.Google Scholar
- Lee, Y., Waterman, A., Cook, H., Zimmer, B., Keller, B., Puggelli, A. ... and Chiu, P. An agile approach to building RISC-V microprocessors. IEEE Micro 36, 2 (Feb. 2016), 8--20. Google ScholarDigital Library
- Leiserson, C. et al. There's plenty of room at the top. To appear.Google Scholar
- Metz, C. Big bets on A.I. open a new frontier for chip start-ups, too. The New York Times (Jan. 14, 2018).Google Scholar
- Moore, G. Cramming more components onto integrated circuits. Electronics 38, 8 (Apr. 19, 1965), 56--59.Google Scholar
- Moore, G. No exponential is forever: But 'forever' can be delayed! {semiconductor industry}. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (San Francisco, CA, Feb. 13). IEEE, 2003, 20--23.Google Scholar
- Moore, G. Progress in digital integrated electronics. In Proceedings of the International Electronic Devices Meeting (Washington, D.C., Dec.). IEEE, New York, 1975, 11--13.Google Scholar
- Nvidia. Nvidia Deep Learning Accelerator (NVDLA), 2017; http://nvdla.org/Google Scholar
- Patterson, D. How Close is RISC-V to RISC-I? ASPIRE blog, June 19, 2017; https://aspire.eecs.berkeley.edu/2017/06/how-close-is-risc-v-to-risc-i/Google Scholar
- Patterson, D. RISCy history. Computer Architecture Today blog, May 30, 2018; https://www.sigarch.org/riscy-history/Google Scholar
- Patterson, D. and Waterman, A. The RISC-V Reader: An Open Architecture Atlas. Strawberry Canyon LLC, San Francisco, CA, 2017. Google ScholarDigital Library
- Rowen, C., Przbylski, S., Jouppi, N., Gross, T., Shott, J., and Hennessy, J. A pipelined 32b NMOS microprocessor. In Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (San Francisco, CA, Feb. 22--24) IEEE, 1984, 180--181.Google Scholar
- Schwarz, M., Schwarzl, M., Lipp, M., and Gruss, D. Netspectre: Read arbitrary memory over network. arXiv preprint, 2018; https://arxiv.org/pdf/1807.10535.pdfGoogle Scholar
- Sherburne, R., Katevenis, M., Patterson, D., and Sequin, C. A 32b NMOS microprocessor with a large register file. In Proceedings of the IEEE International Solid-State Circuits Conference (San Francisco, CA, Feb. 22--24). IEEE Press, 1984, 168--169.Google ScholarCross Ref
- Thacker, C., MacCreight, E., and Lampson, B. Alto: A Personal Computer. CSL-79-11, Xerox Palo Alto Research Center, Palo Alto, CA, Aug. 7,1979; http://people.scs.carleton.ca/~soma/distos/fall2008/alto.pdfGoogle Scholar
- Turner, P., Parseghian, P., and Linton, M. Protecting against the new 'L1TF' speculative vulnerabilities. Google blog, Aug. 14, 2018; https://cloud.google.com/blog/products/gcp/protectingagainst-the-new-l1tf-speculative-vulnerabilitiesGoogle Scholar
- Van Bulck, J. et al. Foreshadow: Extracting the keys to the Intel SGX kingdom with transient out-of-order execution. In Proceedings of the 27<sup>th</sup> USENIX Security Symposium (Baltimore, MD, Aug. 15--17). USENIX Association, Berkeley, CA, 2018. Google ScholarDigital Library
- Wilkes, M. and Stringer, J. Micro-programming and the design of the control circuits in an electronic digital computer. Mathematical Proceedings of the Cambridge Philosophical Society 49, 2 (Apr. 1953), 230--238.Google ScholarCross Ref
- XLA Team. XLA -- TensorFlow. Mar. 6, 2017; https://developers.googleblog.com/2017/03/xlatensorflow-compiled.htmlGoogle Scholar
Index Terms
- A new golden age for computer architecture
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