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Designing a high performance parallel logic programming system

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Published:01 March 1987Publication History
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Abstract

Compilation techniques such as those portrayed by the Warren Abstract Machine (WAM) have greatly improved the speed of execution of logic programs. The research presented herein is geared towards providing additional performance to logic programs through the use of parallelism, while preserving the conventional semantics of logic languages. Two areas to which special attention is given are the preservation of sequential performance and storage efficiency, and the use of low overhead mechanisms for controlling parallel execution. Accordingly, the techniques used for supporting parallelism are efficient extensions of those which have brought high inferencing speeds to sequential implementations. At a lower level, special attention is also given to design and simulation detail and to the architectural implications of the execution model behavior. This paper offers an overview of the basic concepts and techniques used in the parallel design, simulation tools used, and some of the results obtained to date.

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                    cover image ACM SIGARCH Computer Architecture News
                    ACM SIGARCH Computer Architecture News  Volume 15, Issue 1
                    March 1987
                    83 pages
                    ISSN:0163-5964
                    DOI:10.1145/25372
                    Issue’s Table of Contents

                    Copyright © 1987 Authors

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                    Association for Computing Machinery

                    New York, NY, United States

                    Publication History

                    • Published: 1 March 1987

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