NVSim-VX^s: an improved NVSim for variation aware STT-RAM simulation

ABSTRACT

Spin-transfer torque random access memory (STT-RAM) recently received significant attentions for its promising characteristics in cache and memory applications. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. In this work, we introduce a new member of NVSim family -- NVSim-VX^s, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption. This enhanced model takes into account the impacts of parametric variabilities of CMOS and MTJ devices and the chip operating temperature. It is also calibrated with Monte-Carlo Simulations based on macro-magnetic and SPICE models, covering five technology nodes between 22nm and 90nm. NVSim-VX^s strongly supports the fast-growing needs of STT-RAM research on reliability analysis and enhancement, announcing the next important stage of NVSim development.

References

1. S. Arcaro, S. Di Carlo, M. Indaco, D. Pala, P. Prinetto, E. Vatajelu, et al. Integration of stt-mram model into cacti simulator. In International Design & Test Symposium, pages 67--72. IEEE, 2014.
2. Y. Chen, X. Wang, H. Li, H. Xi, Y. Yan, and W. Zhu. Design margin exploration of spin-transfer torque ram (stt-ram) in scaled technologies. IEEE Transactions on Very Large Scale Integration (VLSI) System, 18(12):1724--1734, 2010.
3. Y.-C. Chen, H. Li, W. Zhang, and R. E. Pino. The 3-d stacking bipolar rram for high density. IEEE Transactions on Nanotechnology, 11(5):948--956, 2012.
4. X. Dong, C. Xu, Y. Xie, and N. P. Jouppi. Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(7):994--1007, 2012.
5. E. Eken, Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. A novel self-reference technique for stt-ram read and write reliability enhancement. IEEE Transactions on Magnetics, 50(11):1--4, 2014.
6. R. Kanj, R. Joshi, and S. Nassif. Mixture importance sampling and its application to the analysis of sram designs in the presence of rare failure events. In Design Automation Conference, pages 69--72. ACM, 2006.
7. M. Motoyoshi, I. Yamamura, W. Ohtsuka, M. Shouji, H. Yamagishi, M. Nakamura, H. Yamada, K. Tai, T. Kikutani, T. Sagara, et al. A study for 0.18μm high-density mram. In Symposium on VLSI Technology, pages 22--23, 2004.
8. P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. Technical report, Compaq Computer Corporation, 2001.
9. P. Wang, E. Eken, W. Zhang, R. Joshi, R. Kanj, and Y. Chen. A thermal and process variation aware mtj switching model and its applications in soft error analysis. In More than Moore Technologies for Next Generation Computer Design, pages 101--125. Springer, 2015.
10. W. Wen, Y. Zhang, Y. Chen, Y. Wang, and Y. Xie. Ps3-ram: a fast portable and scalable statistical stt-ram reliability analysis method. In Design Automation Conference, pages 1191--1196. ACM, 2012.
11. B. Wu, Y. Cheng, Y. Wang, A. Todri-Sanial, G. Sun, L. Torres, and W. Zhao. An architecture-level cache simulation framework supporting advanced pma stt-mram. In Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on, pages 7--12. IEEE, 2015.
12. W. Xu, Y. Chen, X. Wang, and T. Zhang. Improving stt mram storage density through smaller-than-worst-case transistor sizing. In Design Automation Conference, pages 87--90. ACM, 2009.
13. Y. Zhang, I. Bayram, Y. Wang, H. Li, and Y. Chen. Adams: asymmetric differential stt-ram cell structure for reliable and high-performance applications. In International Conference on Computer-Aided Design, pages 9--16. IEEE Press, 2013.
14. Y. Zhang, X. Wang, and Y. Chen. Stt-ram cell design optimization for persistent and non-persistent error rate reduction: a statistical design view. In International Conference on Computer-Aided Design, pages 471--477. IEEE Press, 2011.